PDF IDT74ALVCH16270 Data sheet ( Hoja de datos )

Número de pieza	IDT74ALVCH16270
Descripción	3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
Fabricantes	Integrated Device Technology
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No Preview Available ! IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER INDUSTRIALTEMPERATURERANGE 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74ALVCH16270 FEATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range www.Data•ShVeCeCt4=U.2c.o5mV ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in SSOP, TSSOP, and TVSOP packages DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems DESCRIPTION: This registered bus exchanger is built using advanced dual metal CMOS technology. The ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. This device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL)lineselects1Bor2BdatafortheAoutputs.Fordatatransferinthe A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storageregisterintheA-to-2Bpath.PropercontroloftheCLKENA inputallows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). The control terminals are registered to synchronize the bus-direction changes with CLK. The ALVCH16270 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16270 has “bus-hold” which retains the inputs’ last state when- ever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. FUNCTIONAL BLOCK DIAGRAM CLK 29 2 CLKEN1B 27 CLKEN2B 30 CLKENA1 CLKENA2 55 56 OEB 28 SEL 1 OEA 1D C1 A1 8 0 1 CE C1 1D 1 of 12 Channels The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 1999 Integrated Device Technology, Inc. 1 C1 1D CE C1 1D CE C1 1D CE C1 1D CE C1 1D 23 1B1 6 2B1 AUGUST 1999 DSC-4475/1 1 page IDT74ALVCH16270 3.3V CMOS 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER SWITCHING CHARACTERISTICS(1) Symbol Parameter fMAX tPLH PropagationDelay tPHL CLK to xBx tPLH PropagationDelay tPHL CLK to Ax tPLH PropagationDelay tPHL SEL to Ax tPZH OutputEnableTime www.DataShetePtZ4LU.com CLK to xBx tPZH OutputEnableTime tPZL CLK to Ax tPHZ OutputDisableTime tPLZ CLK to xBx tPHZ OutputDisableTime tPLZ CLK to Ax tSU Set-up Time, Ax data before CLK↑ tSU Set-up Time, Bx data before CLK↑ tSU Set-up Time, CLKENA1 or CLKENA2 before CLK↑ tSU Set-up Time, CLKEN1B or CLKEN2B before CLK↑ tSU Set-up Time, OEB or OEA before CLK↑ tH Hold Time, Ax data after CLK↑ tH Hold Time, Bx data after CLK↑ tH Hold Time, CLKENA1 or CLKENA2 after CLK↑ tH Hold Time, CLKEN1B or CLKEN2B after CLK↑ tH Hold Time, OEB or OEA after CLK↑ tW Pulse Width, CLK HIGH or LOW tSK(O) Output Skew(2) VCC = 2.5V ± 0.2V Min. Max. 150 — 1.5 5.9 1.2 5.4 1.4 6.2 1.5 7 1.5 7 1.9 7.2 1.9 7.2 4.1 — 0.9 — 3.5 — 3.4 — 4.4 — 0— 1.4 — 0— 0— 0— 3.3 — —— NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. INDUSTRIALTEMPERATURERANGE VCC = 2.7V Min. Max. 150 — — 5.8 VCC = 3.3V ± 0.3V Min. Max. 150 — 1.1 5.1 Unit MHz ns — 5.4 1 4.7 ns — 6.4 1 5.5 ns — 6.8 1 6 ns — 6.8 1 6 ns — 6.5 1.1 5.8 ns — 6.5 1.1 5.8 ns 3.8 — 3.1 — ns 1.2 — 0.9 — ns 3.2 — 2.7 — ns 3 — 2.6 — ns 3.9 — 3.2 — ns 0 — 0.2 — ns 1 — 1.7 — ns 0.1 — 0.3 — ns 0 — 0.6 — ns 0 — 0.1 — ns 3.3 — 3.3 — ns — — — 500 ps 5 5 Page

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