PDF IDT74ALVCH162344 Data sheet ( Hoja de datos )

Número de pieza	IDT74ALVCH162344
Descripción	3.3V CMOS 1-BIT TO 4-BIT ADDRESS DRIVER
Fabricantes	Integrated Device Technology
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No Preview Available ! IDT74ALVCH162344 3.3V CMOS 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS 3.3V CMOS 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS AND BUS-HOLD INDUSTRIALTEMPERATURERANGE IDT74ALVCH162344 FEATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range www.Data•ShVeCeCt4=U.2c.o5mV ± 0.2V • CMOS power levels (0.4µ W typ. static) • Rail-to-Rail output swing for increased noise margin • Available in SSOP, TSSOP, and TVSOP packages DRIVE FEATURES: • Balanced Output Drivers: ±12mA • Low switching noise DESCRIPTION: This 1-bit to 4-bit address driver is built using advanced dual metal CMOS technology. The ALVCH162344 device is used in applications in which four separate memory locations must be addressed by a single address. The ALVCH162344 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. The ALVCH162344 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high-impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1A 8 1 OE1 2A 14 2 1B1 6 1B4 9 2B1 13 2B4 36 5A 42 6A 29 OE3 3A 15 28 OE2 4A 21 16 3B1 20 3B4 23 4B1 27 4B4 43 7A 8A 49 56 OE4 34 5B1 30 5B4 41 6B1 37 6B4 48 7B1 44 7B4 55 8B1 51 8B4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 1999 Integrated Device Technology, Inc. 1 MARCH 1999 DSC-4563/1 1 page IDT74ALVCH162344 3.3V CMOS 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS INDUSTRIALTEMPERATURERANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS Symbol VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VLOAD 6 6 VIH 2.7 2.7 VT 1.5 1.5 VLZ 300 300 VHZ 300 300 CL 50 50 VCC(2)= 2.5V±0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF www.DataSheet4U.com VCC VLOAD Open Pulse(1, 2) Generator VIN VOUT D.U.T. 500Ω GND RT 500Ω CL ALVC Link Test Circuit for All Outputs DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open SAME PHASE INPUT TRANSITION OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPLH tPHL tPHL Propagation Delay VIH VT 0V VOH VT VOL VIH VT 0V ALVC Link CONTROL INPUT ENABLE tPZL DISABLE tPLZ OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT NORMALLY SWITCH OPEN HIGH VLOAD/2 VT tPHZ VT 0V VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V ALVC Link Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL tSU tH tREM VIH VT 0V VIH VT 0V VIH VT 0V SYNCHRONOUS CONTROL tSU tH VIH VT 0V ALVC Link INPUT OUTPUT 1 OUTPUT 2 tPLH1 tPHL1 tSK (x) tSK (x) VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 5 Set-up, Hold, and Release Times LOW-HIGH-LOW PULSE H IG H -LOW -H IG H PULSE tW Pulse Width VT VT ALVC Link 5 Page

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