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PDF LH28F004SU-NC Data sheet ( Hoja de datos )

Número de pieza LH28F004SU-NC
Descripción 4M (512K bb 8) Flash Memory
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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No Preview Available ! LH28F004SU-NC Hoja de datos, Descripción, Manual

LH28F004SU-NC
4M (512K × 8) Flash Memory
FEATURES
512K × 8 Word Configuration
5 V Write/Erase Operation (5 V VPP)
– No Requirement for DC/DC Converter
to Write/Erase
80 ns Maximum Access Time
32 Independently Lockable Blocks (16K)
100,000 Erase Cycles per Block
Automated Byte Write/Block Interface
– Command User Interface
– Status Register
– RY /» BY » Status Output
System Performance Enhancement
– Erase Suspend for Read
– Two-Byte Write
– Full Chip Erase
Data Protection
– Hardware Erase/Write Lockout during
Power Transitions
– Software Erase/Write Lockout
• Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)
5 µA (Typ.) ICC in CMOS Standby
0.2 µA (Typ.) Deep Power-Down
State-of-the-Art 0.45 µm ETOX™ Flash
Technology
40-Pin, 1.2 mm × 10 mm × 20 mm
TSOP (Type I) Package
40-PIN TSOP
TOP VIEW
A16
A15
A14
A13
A12
A11
A9
A8
WE
RP
VPP
RY/BY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 A17
39 GND
38 NC
37 NC
36 A10
35 DQ7
34 DQ6
33 DQ5
32 DQ4
31 VCC
30 VCC
29 NC
28 DQ3
27 DQ2
26 DQ1
25 DQ0
24 OE
23 GND
22 CE
21 A0
28F004SUT-NC80-1
Figure 1. TSOP Configuration
1

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LH28F004SU-NC pdf
4M (512K × 8) Flash Memory
LH28F004SU-NC
The LH28F004SU-NC contains Status Register to
accomplish various functions:
A Compatible Status Register (CSR) which is 100%
compatible with the LH28F008SA Flash memory’s
Status Register.This register, when used alone, pro-
vides a straightforward upgrade capability to the
LH28F004SU-NC from a LH28F008SA based design.
The LH28F004SU-NC incorporates an open drain
RY »/BY » output pin. This feature allows the user to OR-
tie many RY »/BY » pins together in a multiple memory
configuration such as a Resident Flash Array.
The LH28F004SU-NC is specified for a maximum
access time of 80 ns (tACC) at 5 V operation (4.5 to
5.5 V) over the commercial temperature range (0 to
+70°C).
The LH28F004SU-NC incorporates an Automatic
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical ICC current is 2 mA at 5.0 V.
A Deep Power-Down mode of operation is invoked
when the RP » (called PWD on the LH28F008SA) pin
transitions low, any current operation is aborted and the
device is put into the deep power down mode.This mode
brings the device power consumption to less than 5 µA,
and provides additional write protection by acting as a
device reset pin during power transitions. When the
power is turned on, RP » pin is turned to low in order to
return the device to default configuration. When the
power transition is occurred, or at the power on/off, RP »
is required to stay low in order to protect data from noise.
A recovery time of 550 ns is required from RP » switch-
ing high until outputs are again valid. In the Deep Power-
Down state, the WSM is reset (any current operation
will abort) and the CSR register is cleared.
A CMOS Standby mode of operation is enabled when
CE » transitions high and RP » stays high with all input
control pins at CMOS levels. In this mode, the device
draws an ICC standby current of 10 µA.
MEMORY MAP
7FFFFH
7C000H
7BFFFH
78000H
77FFFH
74000H
73FFFH
70000H
6FFFFH
6C000H
6BFFFH
68000H
67FFFH
64000H
63FFFH
60000H
5FFFFH
5C000H
5BFFFH
58000H
57FFFH
54000H
53FFFH
50000H
4FFFFH
4C000H
4BFFFH
48000H
47FFFH
44000H
43FFFH
40000H
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
2B000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
28F004SUT-NC80-3
Figure 4. Memory Map
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LH28F004SU-NC arduino
4M (512K × 8) Flash Memory
LH28F004SU-NC
START
WRITE B0H
READ COMPATIBLE
STATUS REGISTER
CSR.7 = 0
1
CSR.6 = 0
1
WRITE FFH
ERASE COMPLETED
READ ARRAY DATA
DONE NO
READING
YES
WRITE D0H
WRITE FFH
BUS
OPERATION
Write
Read
Standby
Standby
Write
Read
Write
COMMAND
COMMENTS
Erase
Suspend
Read
Array
Erase
Resume
D = B0H
A=X
Q = CSRD
Toggle CE or OE
to update CSRD.
A=X
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Check CSR.6
1 = Erase Suspended
0 = Erase Completed
D = FFH
A=X
Q = AD
Read must be from
block other than the
one suspended.
D = D0H
A=X
See Command Bus Cycle notes for description of codes.
ERASE RESUMED
READ ARRAY DATA
Figure 7. Erase Suspend to Read Array with Compatible Status Register
28F004SUT-NC80-6
11

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