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PDF DFPIC165X Data sheet ( Hoja de datos )
| Número de pieza | DFPIC165X | |
| Descripción | High Performance 8-bit RISC Microcontroller | |
| Fabricantes | Digital Core Design | |
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DFPIC165X
High Performance
8-bit RISC Microcontroller
ver 2.01
OVERVIEW
The DFPIC165X is a low-cost, high per-
formance, 8-bit, fully static soft IP Core, dedi-
cated for operation with fast memory (typi-
cally on-chip). The core has been designed
with a special concern about low power con-
sumption.
The DFPIC165X is software compatible
with the industry standard PIC16C54,
PIC16C55, PIC16C56, PIC16C57 and
PIC16C58. It employs a modified RISC
architecture (2 times faster than original
implementation).
The DFPIC165X have enhanced core
features and configurable hardware stack.
The separate instruction and data buses allow
a 12 bit wide instruction word with the
separate 8 -bit wide data. The DFPIC165X
typically achieve a 2:1 code compression and
a 8:1 speed improvement over other 8-bit
microcontrollers in its class. The Core has 24
I/O lines and an 8-bit timer/counter with an 8-
bit programmable prescaller.
The power-down mode SLEEP allow user
to reduce power consumption. User can wake
up the controller from SLEEP through an user
reset or watchdog overflow. An integrated
Watchdog Timer with it's own clock signal
provides protection against software lock-up.
The DFPIC165X Microcontroller fits
perfectly in applications ranging from high-
speed automotive and appliance motor control
to low-power remote transmitters/receivers,
pointing devices and telecom processors.
Built-in power save mode and small used area
in programmable devices make this IP perfect
for applications applications with space and
power consumption limitations.
DFPIC165X is delivered with fully auto-
mated testbench and complete set of tests
allowing easy package validation at each
stage of SoC design flow.
CPU FEATURES
● Software compatible with industry standard
PIC16C5X
● Harvard architecture 2 times faster com-
pared to original implementation
● 33 instructions
● 12 bit wide instruction word
● Up to 256 bytes of internal Data Memory
● Up to 4K bytes of Program Memory
● Configurable hardware stack
● Power saving SLEEP mode
● Fully synthesizable, static synchronous
design with no internal tri-states
● Scan test ready
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
1 page  
PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
CYCLONE
Speed
grade
Logic Cells
-6 551
Fmax
105 MHz
CYCLONE II -6 547 108 MHz
STRATIX
-5
551
108 MHz
STRATIX II
-3
456
178 MHz
STRATIX GX -5 551 109 MHz
APEX II
-7 635
73 MHz
APEX20KC
-7
635
68 MHz
www.DataSheAetP4UE.Xco2m0KE
-1
635
56 MHz
APEX20K
-1
635
45 MHz
ACEX1K -1 648
50 MHz
FLEX10KE
-1
648
48 MHz
*CPU – consisted of ALU, Control Unit, Bus Controller, Hardware Stack,
256 B RAM, 4k of Program memory
Core performance in ALTERA® devices
IMPROVEMENT
Most instruction of DFPIC165X is executed
within 2 CLK cycles. Except the conditional
program memory branches in case that the
condition of branch instruction is met. The
table below shows sample instructions execu-
tion times:
Mnemonic DFPIC165X PIC16C54
operands (CLK cycles) (CLK cycles)
ADDWF
2
4
ANDWF
2
4
RLF 2 4
BCF
24
DECFSZ
INCFSZ
BTFSC
2(4)1
2(4)1
2(4)1
4(8)1
4(8)1
4(8)1
BTFSS
2(4)1
4(8)1
CALL 2 8
GOTO
2
8
RETLW
2
8
1- number of clock in case that result of operation is 0.
Impr.
2
2
2
2
2
2
2
2
4
4
4
DFPIC&DRPIC FAMILY OVERVIEW
The family of DCD DFPICXX & DRPICXX IP Cores combine a high–performance, low cost, and
small compact size, offering the best price/performance ratio in the IP Market. The DCD’s Cores are
dedicated for use in cost-sensitive consumer products, computer peripherals, office automation,
automotive control systems, security and telecommunication applications.
DCD’s DFPICXX & DRPICXX IP Cores family contains four 8-bit microcontroller Cores to best
meet your needs: DFPIC165X 12-bit program word, DFPIC1655X 14-bit program word, and
DRPIC1655X and DRPIC166X single cycle microcontrollers with 14-bit program word. All three mi-
crocontroller cores are binary compatible with widely accepted PIC16C5X and PIC16CXXX. They
employ a modified RISC architecture two or four times faster than the original ones.
The DFPICXXX & DRPICXX IP Cores are written in pure VHDL/VERILOG HDL languages which
make them technologically independent. All of the DFPICXX & DRPICXX family members supports a
power saving SLEEP mode and allows the user to configure the watchdog time-out period and a
number of hardware stack levels. DFPICXX & DRPICXX can be fully customized according to cus-
tomer needs.
Design
DFPIC165X 2k 128 12 33 24
DFPIC1655X 64k 512 14 35 16
DRPIC1655X 64k 512 14 35 32
DRPIC166X 64k 512 14 35 32
--
--
--
--
--
--
- - 2 - 2 - 2 700
518
2 * 3 900
518
4 * 4 800
558
4 * 6 700
* Optional
DFPIC & DRPIC family of High Performance Microcontroller Cores
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet DFPIC165X.PDF ] | |
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