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PDF C6845 Data sheet ( Hoja de datos )
| Número de pieza | C6845 | |
| Descripción | CRT Controller Megafunction | |
| Fabricantes | Cast | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de C6845 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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C6845
CRT Controller
Megafunction
General Description
The C6845 Cathode Ray Tube Controller (CRTC) interfaces a microprocessor to a raster-scan CRT display.
The C6845 is a synchronous, synthesizable VHDL megafunction, functionally equivalent to the Motorola
www.DataSheet4U.McoCm6845 CRT Controller.
The microprocessor access 19 registers (1 Address and 18 Data Registers) within the C6845 in order to
provide video timing, refresh memory addresses, cursor, and light pen strobe signals. CRT video timing signals
include Vertical Sync (VS), Horizontal Sync (HS), and Display Enable (DE) output signals. Refresh memory
addressing includes Memory Address (MA[13:0]) and Row Address (RA[4:0]) output buses.
The C6845 microprocessor interface consist of unidirectional data input (DIN[7:0]) and data output
(DOUT[7:0]) buses and control signals RS, RWn, CSn, and E. Optionally, an available bus wrapper converts
the unidirectional data buses into an 8-bit bi-directional data bus (D[7:0]). This is the pin equivalent to the
MC6845.
Features
• Fully-synchronous, synthesizable VHDL Megafunction, functionally equivalent to Motorola MC6845
• Capable of driving alphanumeric, semi-graphic, or bit-mapped graphics displays
• Wide range of programmable alphanumeric screen formats
• Programmable registers controlling output signals Vertical Sync (VS), Horizontal Sync (HS), and
Display Enable (DE) signals
• Programmable horizontal line rate and sync pulse width
• Programmable vertical frame rate
• Programmable registers controlling Memory Address (MA[13:0]) start address
• Programmable Start Address Register for Hardware Scrolling
• Programmable registers controlling Row Address (RA[4:0]) size, yielding a character row
• Programmable register controlling Normal Sync (Non-Interlace), Interlace Sync, or Interlace Sync &
Video Mode
• Programmable registers for control and format of Cursor
• Light Pen Register
• Microprocessor 8-bit Data Bus and Control Interface
CAST, Inc.
March 2004
Page 1
1 page  
CAST C6845 Megafunction Datasheet
Start Address
Start Address Register R12 and R13 indicate the first address the Linear Address Generator puts on the Refresh
Memory Address bus at the start of a vertical frame. Whenever the microprocessor writes to R12 and R13, the
Linear Address Generator is updated at the start of the next vertical frame.
Light Pen Register
On the rising edge of the LPSTB input, after synchronization by two CLK cycles, the value of the Refresh
Memory Address bus is captured by the Light Pen Registers R16 and R17. These registers are readable by-way-
of the microprocessor interface.
Linear Address Generator
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The Linear Address Generator generates the Refresh Memory Address. The Linear Address Generator initializes
to the value of the Start Address Registers R12 and R13 at the start of each vertical frame. The Linear Address
Generator remains active during horizontal and vertical retrace, for refresh of dynamic RAMs.
Device Utilization & Performance
Supported
Family
Cyclone
Stratix
Stratix-II
Device
Tested
EP1C20-6
EP1S20-5
EP2S60-3
Utilization
LEs Memory Memory bits
399 0
0
399 0
0
330 0
0
Performance
Fmax
186 MHz
194 MHz
221 MHz
Deliverables
Encrypted Netlist License
• Post synthesis EDIF netlist
• Assignment & Configuration
• Symbol & Include files
• Testbench
• Vectors for testing the functionality of the megafunction
• Place & Route Scripts
• Documentation
CAST, Inc.
Page 5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet C6845.PDF ] | |
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