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PDF LH1560F Data sheet ( Hoja de datos )

Número de pieza LH1560F
Descripción 160 OUTPUT LCD SEGMENT / COMMON DRIVER
Fabricantes Sharp Electrionic Components 
Logotipo Sharp Electrionic Components Logotipo



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No Preview Available ! LH1560F Hoja de datos, Descripción, Manual

1SPEC No. 1 E L 0 6 Xl 0 9 1
I S S U E: Aug. 10. 1995
To;
SPECIFICATIONS
Model No.
LH1560F
%This specifications containsapages
including the cover and appendix.
If you have any objections,please contact us before issuing purchasing order.
CUSTOMERSACCEPTANCE
DATE:
BY:
PRESENTED
Dept. General Manager
REVIEWED BY:
PREPARED BY:
LOGIC
TENRI
SHARP

1 page




LH1560F pdf
1. Block Diagram
LH1560F
3
160 Bits 4-Level Driver
I
I,
I
I
A
%60
160 Bits Level Shifter
Control
160 Bits Lin-
f-l60
r-*-I I=LICC
"
L/R
I
S/C
Di, Di, Di, DI,
VOO vss vss
1. Functional Operations of Each Block
Block
ctive Contra
;P Conversion
L Data Contro
bata Latch
:ontrol
Function
In case of segment mode, controls the selection or deselection
of the chip.
Following a LP signal input, and after the chip select signal is
input, a select signal is generated internally
until 160 bits of
data have been read in.
Once data input has been completed, a select signal for cascade
connection is output. and the chip is deselected.
In case of common mode, controls the input/output
data of bidi-
rectional pins.
In case of segment mode, keep input data which are 2 clocks of
XCK at 4-bit parallel mode into latch circuit, or keep input
data which are 1 clock of XCK at 8-bit parallel mode into latch
circuit.after
that they are put on the internal data bus 8 bits
at a time.
In case of segment mode, selects the state of the data latch
which reads in the data bus signals. The shift direction is
controlled by the control logic, for every 16 bits of data read
in, the selection signal shifts one bit based on the state of
the control circuit.

5 Page





LH1560F arduino
SHARP
LHl560F
9
EIO,
EIOp
yI-ylso
*When set to VDD level ‘H”.segment mode is set.
Input/Output
pin for chip selection
*When L/R input is at VSS level “L”, EIO, is set for output, and EIO:
is set for input.
*When L/R input is at Voo level “H”, EIO, is set for input, and EIOz
is set for output.
*During output. set to “H” while LP*E is “H” and after 160-bits of
data have been read, set to “L” for one cycle (from falling edge to
falling edge of XCK). after which it returns to “H”.
*During input. after the LP signal is input, the chip is selected
while EI is set to “L”. After 160-bits of data have been read, the
chip is deselected.
LC driver output pins
*Corresponding directly to each bit of the data latch, one level
(Vo. VIZ? v43* or VSS> is selected and output.
Table of truth values is shown in 7-2-l.
V~~R.V,~~
v43R* V43L
rEIO,
I
EIOz
LP
L/R
*Normally. the bias voltage used is set by a resistor divider.
*Ensure that voltages are set such that VSS<V43<V,z<Vo.
*To further reduce the difference between the output waveforms of LC
driver output pins Y, and YIBo, externally connect ViR and V,L
(i=O. 12, 43).
Bidirectional
shift register shift data input/output
pin
*Output pin when L/R is at VSS level “L”. input pin when L/R is at
VDo level “H”.
*When EIO, is used as input pin, it will be pull-doen.
-When EIO, is used as output pin,it won’t be pull-down.
Bidirectional
shift register shift data input/output
pin
*Input pin when L/R is at VSS level “L”. output pin when L/R is at
VDD level “H”.
*When EIOz is used as input pin, it will be pull-down.
*When EIOp is used as output pin, it won’t be pull-down.
Bidirectional
shift register shift clock pulse input pin
*Data is shifted on the falling edge of the clock pulse.
Bidirectional
shift register shift direction selection pin
*Data is shifted from Ylso to Y, when set to VSS level “L”. and data
is shifted from Y, to Ytso when set to VDo level “H”.

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