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PDF P5NK80Z Data sheet ( Hoja de datos )

Número de pieza P5NK80Z
Descripción STP5NK80Z
Fabricantes STMicroelectronics 
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No Preview Available ! P5NK80Z Hoja de datos, Descripción, Manual

STP5NK80Z
STP5NK80ZFP
N-channel 800V - 1.9- 4.3A - TO-220/TO-220FP
Zener-protected SuperMESH™ Power MOSFET
General features
www.DataSheet4U.com Type
STP5NK80Z
STP5NK80ZFP
VDSS
(@Tjmax)
800 V
800 V
RDS(on)
< 2.4
< 2.4
ID
4.3 A
4.3 A
100% avalanche tested
Gate charge minimized
Very low intrinsic capacitances
Very good manufacturing repeatibility
Description
The SuperMESH™ series is obtained through an
extreme optimization of ST’s well established
strip-based PowerMESH™ layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh™ products.
Applications
Switching application
TO-220
3
2
1
TO-220FP
Internal schematic diagram
Order codes
Part number
STP5NK80Z
STP5NK80ZFP
Marking
P5NK80Z
P5NK80ZFP
Package
TO-220
TO-220FP
Packaging
Tube
Tube
August 2006
Rev 4
1/15
www.st.com
15

1 page




P5NK80Z pdf
STP5NK80Z - STP5NK80ZFP
2 Electrical characteristics
Electrical characteristics
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(TCASE=25°C unless otherwise specified)
Table 5. On/off states
Symbol
Parameter
Test conditions
V(BR)DSS
Drain-source breakdown
voltage
ID = 1mA, VGS= 0
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = Max rating,
VDS = Max rating,
Tc = 125°C
IGSS
VGS(th)
RDS(on)
Gate body leakage current
(VGS = 0)
VGS = ± 20V
Gate threshold voltage
VDS = VGS, ID = 100µA
Static drain-source on
resistance
VGS = 10V, ID = 2.15 A
Min. Typ. Max. Unit
800 V
1 µA
50 µA
±10 µA
3 3.75 4.5 V
1.9 2.4
Table 6. Dynamic
Symbol
Parameter
Test conditions
Min. Typ. Max. Unit
gfs (1)
Ciss
Coss
Crss
Forward transconductance VDS =15V, ID = 2.15A
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS =25V, f=1 MHz, VGS=0
4.25
910
98
20
S
pF
pF
pF
Cosseq(2).
Equivalent output
capacitance
VGS=0, VDS =0V to 400V
40
pF
td(on)
tr
td(off)
tr
Qg
Qgs
Qgd
td(Voff)
tr
Turn-on delay time
Rise time
Turn-on delay time
fall time
Total gate charge
Gate-source charge
Gate-drain charge
Off-voltage rise time
Fall time
Cross-over time
VDD=400 V, ID= 2 A,
RG=4.7Ω, VGS=10V
(see Figure 18)
VDD=640V, ID = 4.3A
VGS =10V
VDD=640 V, ID= 4.3 A,
RG=4.7Ω, VGS=10V
(see Figure 20)
18
25
45
30
32.4 45.5
5
18.5
22
10
32
ns
ns
ns
ns
nC
nC
nC
ns
ns
ns
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
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P5NK80Z arduino
STP5NK80Z - STP5NK80ZFP
4 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
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