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PDF IDT71P71804 Data sheet ( Hoja de datos )

Número de pieza IDT71P71804
Descripción (IDT71P71604 / IDT71P71804) 18Mb Pipelined DDRII SRAM Burst of 2
Fabricantes IDT 
Logotipo IDT Logotipo



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No Preview Available ! IDT71P71804 Hoja de datos, Descripción, Manual

18Mb Pipelined
DDR™II SRAM
Burst of 2
IDT71P71804
IDT71P71604
Features
18Mb Density (1Mx18, 512kx36)
Common Read and Write Data Port
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
Multiplexed Address Bus
www.DataSheet4U.com
- One Read or One Write request per clock cycle
DDR (Double Data Rate) Data Bus
- Two word bursts data per clock
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals from
1.4V to 1.9V.
Scalable output drivers
- Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
- Output Impedance adjustable from 35 ohms to 70
ohms
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Description
The IDT DDRIITM Burst of two SRAMs are high-speed synchro-
nous memories with a double-data-rate (DDR), bidirectional data port.
This scheme allows maximization of the bandwidth on the data bus by
passing two data items per clock cycle. The address bus operates at
single data rate speeds, allowing the user to fan out addresses and
ease system design while maintaining maximum performance on data
transfers.
The DDRII has scalable output impedance on its data output bus
and echo clocks, allowing the user to tune the bus for low noise and high
performance.
All interfaces of the DDRII SRAM are HSTL, allowing speeds
beyond SRAM devices that use any form of TTL interface. The inter-
face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
Clocking
The DDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the DDRII has an output “echo”
clock, CQ, CQ.
Functional Block Diagram
DATA
REG
(Note2)
SA
SA0
ADD
REG
(Note2)
LD
R/W
BW x
(Note3)
CTRL
LOGIC
(Note 1)
WRITE DRIVER
18M
MEMORY
ARRAY
(Note1)
(Note4)
(Note1) DQ
K CLK
K GEN
C SELECT OUTPUT CONTROL
C
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x18 and 19 address signal lines for x36.
3) Represents 2 signal lines for x18 and 4 signal lines for x36.
4) Represents 36 signal lines for x18 and 72 signal lines for x36.
6112 drw 16
CQ
CQ
APRIL 2006
1
©2006 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6112/0A

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IDT71P71804 pdf
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Pin Configuration IDT71P71804 (1M x 18)
Commercial Temperature Range
1 2 3 4 5 6 7 8 9 10 11
A
CQ
VSS/
SA (2)
SA
R/W
BW 1
K
NC
LD
SA
VSS/
SA (1)
CQ
B NC DQ9 NC SA NC K BW 0 SA NC NC DQ8
C NC NC NC VSS SA SA0 SA VSS NC DQ7 NC
D NC NC DQ10 VSS VSS VSS VSS VSS NC NC NC
www.DataSheet4U.com
E
NC
NC
DQ11 VDDQ
VSS
VSS
VSS VDDQ
NC
NC DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD VDDQ
NC
NC DQ5
G
NC
NC
DQ13
VDDQ
VDD
VSS
VDD VDDQ
NC
NC
NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J NC NC NC VDDQ VDD VSS VDD VDDQ NC DQ4 NC
K
NC
NC
DQ14
VDDQ
VDD
VSS
VDD VDDQ
NC
NC DQ3
L
NC
DQ15
NC
VDDQ
VSS
VSS
VSS VDDQ
NC
NC DQ2
M NC NC NC VSS VSS VSS VSS VSS NC DQ1 NC
N
NC
NC DQ16 VSS
SA
SA
SA VSS
NC
NC
NC
P NC NC DQ17 SA SA C SA SA NC NC DQ0
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
165-ball FBGA Pinout
TOP VIEW
6112 tbl 12b
NOTES:
1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to Vss on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 2 (71P71804) devices.
6.542

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IDT71P71804 arduino
IDT71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)
18 Mb DDR II SRAM Burst of 2
Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
PARAMETER
SYMBOL
MIN
MAX UNIT NOTES
Input High Voltage, DC
VIH (DC)
VREF +0.1
VDDQ +0.3
V
1,2
Input Low Voltage, DC
VIL (DC)
-0.3
VREF -0.1
V
1,3
Input High Voltage, AC
VIH (AC)
VREF +0.2
-
V 4,5
Input Low Voltage, AC
VIL (AC)
-
VREF -0.2
V
4,5
NOTES:
6112 tbl 10d
1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.
2. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))
www.DataSheet34. UV.IHco(Mmax) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))
4. This conditon is for AC function test only, not for AC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)
b) Reach at leaset the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overshoot Timing
VDD +0.5
VDD +0.25
VDD
20% tKHKH (MIN)
VIL
Undershoot Timing
VIH
VSS
VSS-0.25V
VSS-0.5V
6112 drw 21
20% tKHKH (MIN)
6112 drw 22
61.412

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