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PDF YSS901 Data sheet ( Hoja de datos )

Número de pieza YSS901
Descripción SD Stereo dipole
Fabricantes YAMAHA CORPORATION 
Logotipo YAMAHA CORPORATION Logotipo



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No Preview Available ! YSS901 Hoja de datos, Descripción, Manual

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YSS901
SD
Stereo dipole
Preliminary
g Outline
YSS901 is a device that uses the stereo dipole system (SD) with which the transaural system can be constructed.
When a stereophonic signal that has been processed with the SD system of this device is inputted to two
speakers located adjacently at the center of the field (or to two speakers contained in one cabinet), the virtual
sound positioning function of this system produces the stereophonic sound similar to the one that can be
obtained by using an ordinary stereophonic sound replay system through the central two speakers.
YSS901 has built-in one bit Delta-Sigma type A/D and D/A converters for each of the two channels at its input
and output respectively. Thanks to these built-in converters, this device can process analog stereophonic sound
signal through the converters in addition to digital stereophonic sound signal.
This device performs an advanced convolution through DSP using the FIR filter.
g Features
n Two channel virtual sound positioning by using the stereo dipole system.
n Processes analog or digital signals at each of the two channels.
n Four types of digital data format are available, including 48 fs Serial-DAC16, 18 and 20 bits, and 64 fs.
n Six types of parameter coefficients are built in the device. Additional parameter coefficients can be
downloaded externally.
n The parameter control is made through the DC switches or synchronous three-wire serial system.
n Uses a clock of 2.822 MHz from the crystal. External clock can also be used.
n Has a built-in PLL circuit for generating clock for operation.
n Internal operating frequency of 512 fs.
n Allows fading in or out the output of the results of the convolution when switching the coefficient.
n Power supply voltage: 5 V
n Si-gate CMOS process.
n 64 QFP
YAMAHA CORPORATION
YSS901CATALOG
CATALOG No.: LSI-4SS901A0
1999. 1

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YSS901 pdf
YSS901
g Outline of Functions
1. Clock signals
XTAL, EXTAL and PLLC
For the clock signal, use the crystal connected to XTAL EXTAL pin with which the clock signal is obtained by the
self-oscillation at the crystal oscillation circuit, or external signal supplied through EXTAL pin. The frequency of the
clock obtained by the self-oscillation is 2.822 MHz (or 44.1 kHz * 64). The internal operation is carried out with 512
fs clock that is made by the PLL.
Insert an analog filter in between PLLC and GND pins.
2. Data input/output signals
Analog/digital input selection pin: DSEL2
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This pin is used to select a type of the input signal. DSEL2 = 0 selects the digital signal input, or DSEL2 = 1 selects
the analog signal input.
2-1) Digital signal
Digital signal input/output pins: DIN, BCLK, SYNCN and DOUT
Digital signals should be inputted through DIN, BCLK and SYNCN pins.
DIN signal (PCM data) must be in synchronous with BCLK (bit clock) and SYNCN (word clock) signals.
Digital signal is outputted from DOUT pin.
Input/output format designation pins: DSEL1 and DSEL0
These pins are used to designate a data format for DAC. The settings of DSEL1 and DSEL0 and their output formats
are as follows.
DSEL1
0
0
1
1
DSEL0
0
1
0
1
DAC output format
48 fs 16 bits Data LSB justified
48 fs 18 bits Data LSB justified (Bits 1 and 0 are “0”.)
48 fs 20 bits Data LSB justified (Bits 3 through 0 are “0”.)
64 fs 16 bits Data MSB justified (Delay by one bit)
For the details of the format, refer to “Serial Data Interface” explained later in this document.
2-2) Analog signal
Analog input/output pins:
AIL, AILOUT, AILRET, LOUT, AIR, AIROUT, AIRRET and ROUT
Analog signals should be inputted through AIL and AIR pins. The signals that have been processed by the stereo
dipole (SD) are outputted from LOUT and ROUT pins respectively. Add an analog filter circuit, an example of
which is shown later in this document.
Center voltage pin
VREF
This pin outputs a reference voltage for analog signal processing. Connect an appropriate capacitor between VREF
and GND pins.
3. Controlling functions
3-1) Control method selection pin: CTLSEL
This pin is used for selection of a control method as described below.
CTLSEL = 0 : Selection of CSEL2, CSEL1 or CSEL0 by means of DC switch (H/L) is enabled.
CTLSEL = 1 : Selection of CSN, SI or SCK through the microcomputer is enabled.
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YSS901 arduino
YSS901
g Design Example
The figure below shows basic design example that uses YSS901.
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N.C
N.C
N.C
N.C
LOUT
470p 10k
ROUT
PLLC
22p
2.8224M
22p
1M
680
AVSS
EXTAL
XTAL
DVSS
TSTCK
TST1
TSTNI
TSTNO
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
DVDD
DSEL0
DSEL1
DSEL2
DIN
DOUT
CSN
BCLK
SYNCN
CTLSEL
DVDD
N.C
N.C
N.C
N.C
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