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PDF M37221EFSP Data sheet ( Hoja de datos )

Número de pieza M37221EFSP
Descripción SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fabricantes Mitsubishi Electric Semiconductor 
Logotipo Mitsubishi Electric Semiconductor Logotipo



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MITSUBISHI MICROCOMPUTERS
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
DESCRIPTION
The M37221EF-XXXSP and M37221EFSP are single-chip microcom-
puters designed with CMOS silicon gate technology. They are housed
in a 42-pin shrink plastic molded DIP.
In addition to their simple instruction sets, the ROM, RAM and I/O
addresses are placed on the same memory map to enable easy pro-
gramming.
The M37221EF-XXXSP and M37221EFSP have a PWM output func-
tion and a OSD display function, so it is useful for a channel selection
system for TV.
www.DataSheet4U.com
FEATURES
Number of basic instructions ..................................................... 71
Memory size
ROM ........................................................ 62 K bytes
RAM ....................................................... 1216 bytes
ROM for display ......................................... 8 K bytes
RAM for display .......................................... 96 bytes
The minimum instruction execution time
......................................... 0.5 µs (at 8 MHz oscillation frequency)
Power source voltage .................................................. 5 V ± 10 %
Power dissipation............................................................. 165 mW
(at 8 MHz oscillation frequency, VCC=5.5V, at CRT display)
Subroutine nesting ....................................... 96 levels (maximum)
Interrupts ....................................................... 14 types, 14 vectors
8-bit timers .................................................................................. 4
Programmable I/O ports (Ports P0, P1, P2, P30–P32) .............. 27
Input ports (Ports P33, P34) ......................................................... 2
Output ports (Ports P52–P55) ...................................................... 4
12 V withstand ports .................................................................... 6
LED drive ports ........................................................................... 4
Serial I/O ............................................................ 8-bit ! 1 channel
Multi-master I2C-BUS interface ............................... 1 (2 systems)
A-D comparator (6-bit resolution) ................................ 6 channels
D-A converter (6-bit resolution) ................................................... 2
PWM output circuit ......................................... 14-bit ! 1, 8-bit ! 6
ROM correction function ........................................... 32 bytes ! 2
PIN CONFIGURATION (TOP VIEW)
HSYNC
VSYNC
P00/PWM0
P01/PWM1
P02/PWM2
P03/PWM3
P04/PWM4
P05/PWM5
P06/INT2/A-D4
P07/INT1
P23/TIM3
P24/TIM2
P25
P26
P27
D-A
P32
CNVSS
XIN
XOUT
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 P52/R
41 P53/G
40 P54/B
39 P55/OUT1
38 P20/SCLK
37 P21/SOUT
36 P22/SIN
35 P10/OUT2
34 P11/SCL1
33 P12/SCL2
32 P13/SDA1
31 P14/SDA2
30 P15/A-D1/INT3
29 P16/A-D2
28 P17/A-D3
27 P30/A-D5/DA1
26 P31/A-D6/DA2
25 RESET
24 OSC1/P33
23 OSC2/P34
22 VCC
Outline 42P4B
CRT display function
Number of display characters ................ 24 characters ! 2 lines
(16 lines maximum)
Kinds of characters ..................................................... 256 kinds
Dot structure .......................................................... 12 ! 16 dots
Kinds of character sizes .................................................. 3 kinds
Kinds of character colors (It can be specified by the character)
maximum 7 kinds (R, G, B)
Kinds of character background colors (It can be specified by the character)
maximum 7 kinds (R, G, B)
Kinds of raster colors (maximum 7 kinds)
Display position
Horizontal .................................................................. 64 levels
Vertical .................................................................... 128 levels
Bordering (horizontal and vertical)
APPLICATION
TV

1 page




M37221EFSP pdf
MITSUBISHI MICROCOMPUTERS
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
PIN DESCRIPTION (continued)
P52/R,
P53/G,
P54/B,
P55/OUT1
HSYNC
VSYNC
D-A
Output port P5
CRT output
HSYNC input
VSYNC input
DA output
Output
Output
Input
Input
Output
Ports P52–P55 are a 4-bit output port. The output structure is CMOS output.
Pins P52–P55 are also used as CRT output pins R, G, B, OUT1 respectively. The output
structure is CMOS output.
This is a horizontal synchronizing signal input for CRT.
This is a vertical synchronizing signal input for CRT.
This is a 14-bit PWM output pin.
Note : As shown in the memory map (Figure 3), port P0 is accessed as a memory at address 00C016 of zero page. Port P0 has the port P0
direction register (address
www.DataSheet4U.cpormogrammed as “1” in the
00C116 of zero page)
direction register are
which
output
can be used to program each bit as an input (“0”) or an output (“1”).
pins. When pins are programmed as “0,” they are input pins. When
The pins
pins are
programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the
output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the
output “L” voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the
values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the
floating state.
5

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M37221EFSP arduino
MITSUBISHI MICROCOMPUTERS
M37221EF-XXXSP,M37221EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
with ON-SCREEN DISPLAY CONTROLLER
INTERRUPTS
Interrupts can be caused by 14 different sources consisting of 4 ex-
ternal, 8 internal, 1 software, and reset. Interrupts are vectored inter-
rupts with priorities shown in Table 1. Reset is also included in the
table because its operation is similar to an interrupt.
When an interrupt is accepted,
(1) The contents of the program counter and processor status
register are automatically stored into the stack.
(2) The interrupt disable flag I is set to “1” and the corresponding
interrupt request bit is set to “0.”
www.DataShe(3e)t4TUh.ecojummp destination address stored in the vector address enters
the program counter.
Other interrupts are disabled when the interrupt disable flag is set to
“1.”
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit. The interrupt request bits are
in interrupt request registers 1 and 2 and the interrupt enable bits are
in interrupt control registers 1 and 2. Figure 7 shows the structure of
the interrupt-related registers.
Interrupts other than the BRK instruction interrupt and reset are ac-
cepted when the interrupt enable bit is “1,” interrupt request bit is “1,”
and the interrupt disable flag is “0.” The interrupt request bit can be
set to “0” by a program, but not set to “1.” The interrupt enable bit can
be set to “0” and “1” by a program.
Reset is treated as a non-maskable interrupt with the highest priority.
Figure 6 shows interrupt control.
Interrupt Causes
(1) VSYNC and CRT interrupts
The VSYNC interrupt is an interrupt request synchronized with
the vertical sync signal.
The CRT interrupt occurs after character block display to the CRT
is completed.
(2) INT1, INT2, INT3 interrupts
With an external interrupt input, the system detects that the level
of a pin changes from “L” to “H” or from “H” to “L,” and generates
an interrupt request. The input active edge can be selected by
bits 3, 4 and 5 of the interrupt input polarity register (address
00F916) : when this bit is “0,” a change from “L” to “H” is de-
tected; when it is “1,” a change from “H” to “L” is detected. Note
that all bits are cleared to “0” at reset.
(3) Timer 1, 2, 3 and 4 interrupts
An interrupt is generated by an overflow of timer 1, 2, 3 or 4.
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial
I/O function.
Table 1. Interrupt vector addresses and priority
Interrupt source
Priority
Reset
CRT interrupt
1
2
INT2 interrupt
3
INT1 interrupt
Timer 4 interrupt
4
5
f(XIN)/4096 interrupt
VSYNC interrupt
Timer 3 interrupt
6
7
8
Timer 2 interrupt
Timer 1 interrupt
9
10
Serial I/O interrupt
Multi-master I2C-BUS interface interrupt
INT3 interrupt
11
12
13
BRK instruction interrupt
14
Vector addresses
FFFF16, FFFE16
FFFD16, FFFC16
FFFB16, FFFA16
FFF916, FFF816
FFF516, FFF416
FFF316, FFF216
FFF116, FFF016
FFEF16, FFEE16
FFED16, FFEC16
FFEB16, FFEA16
FFE916, FFE816
FFE716, FFE616
FFE516, FFE416
FFDF16, FFDE16
Remarks
Non-maskable
Active edge selectable
Active edge selectable
Active edge selectable
Active edge selectable
Non-maskable (software interrupt)
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