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PDF TB386 Data sheet ( Hoja de datos )
| Número de pieza | TB386 | |
| Descripción | Implementing the HIP1011 on Hot Swap CPCI Boards | |
| Fabricantes | Intersil Corporation | |
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TM
PRELIMINARY
Implementing the HIP1011 on Hot Swap CPCI
Boards for High Availability (HA) Platforms
Technical Brief
August 2000
TB386
Introduction
The October 1999 release of the CompactPCI Specification
PICMG 2.0 R3.0 defines for the CPCI environment such
developments as 66MHz operation, 3.3V signaling, the
addition of the System Manager, further definition and
differentiation of Hot Swap (PICMG 2.1 R1.0) and improved
mechanical features. Until now, CPCI Hot Swap features
were offered as a vendor proprietary feature with little or no
interoperability.
www.DataShePeItC4UM.Gcom2.1 R1.0 now defines three Hot Swap system
models: Basic, Full and High Availability (HA) each of
increasing complexity and automation. Intersil Tech Brief
TB358 details the implementation of the HIP1011 on boards
for the Basic and Full models. This Tech Brief details
important specification enhancements as they pertain to Hot
Swap and the HIP1011 solution for boards to be used in HA
System platforms.
HA Normal Insertion Sequence
Figure 1 is a simple diagram illustrating the progression of a
normal insertion. A more detailed state diagram can be
found in PICMG 2.1 R1.0 section 2.4. In the following state
diagrams Px = Physical connection state, Hx = Hardware
connection state and Sx = Software connection state.
P0 PHYSICAL BOARD INSERTION
P1 H0
BD_SEL# BOARD SEATED AND
POWERED-ON
H1 H1F
HEALTHY # BOARD REPORTS PGOOD AND
PCI_RST # IS RELEASED FROM PCI RESET
H2 S0
ENUM # ALL HW CONNECTED AND
SW CONNECTION INITIATED
S1
As the board is being connected onto the system bus, the
ground plane and early power are first connected via the
longest pins. The HIP1011 is ground referenced by way of the
GND, PWRON and OCSET pins thus holding off the outputs
during subsequent connection of the medium length pins that
apply the chip and voltage rail bias. Once the system manager
recognizes complete board insertion by the BD_SEL# (shortest
pin) signal being pulled up to V(I/O), it signals that pin low
turning on the HIP1011. With the PWRON, FLTN and the
VOUT asserted, the HEALTHY# is pulled low indicating to the
system manager HW that the board is powered and ready for
use. The PCI_RST# signal is also generated and along with the
Local_PCI_RST# initiates configuration of the remaining Hard
Ware (HW) on the board. Once complete, ENUM# is asserted
by the HW manager and the Soft Ware (SW) configuration
starts, resulting in expected I/O activity. A significant
enhancement from the BASIC AND FULL platforms to the HA
platform is the change from BD_SEL# being hardwired to
ground to being a back plane available signal to the system
controller. Thus the controller can selectively power each and
any board at any time as necessary.
HA Normal Extraction Sequence
Figure 2 illustrates the progression of a normal board
extraction. A more detailed state diagram can be found in
PICMG 2.1 R1.0 section 2.4.
S3 S3Q
S2 S2Q
BOARD EXTRACTION INITIATED BY
EJECTOR HANDLE. SYSTEM MGR
ENUM # DRIVES ENUM# TO INDICATE
IMPENDING EXTRACTION.
OS QUIESCES I/O ACTIVITY
S1
H2 S0
H1 H1F
LED ON
I/O ACTIVITY HALTED
PCI_RST#
LOCAL PCI_RST#
HW DISCONNECTION BY SW
BD_SEL#
HEALTHY #
S2 S2Q
S3 S3Q
SW CONFIGURATION COMPLETED
NORMAL I/O ACTIVITY
P1 H0
PHYSICAL EXTRACTION
FIGURE 1.
P0
FIGURE 2.
1 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
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| Páginas | Total 3 Páginas | |
| PDF Descargar | [ Datasheet TB386.PDF ] | |
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