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PDF ICS1893CF Data sheet ( Hoja de datos )

Número de pieza ICS1893CF
Descripción 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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No Preview Available ! ICS1893CF Hoja de datos, Descripción, Manual

Integrated Device Technology, Inc.
ICS1893CF
Document Type: Data Sheet
Document Stage: Rev. F Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver
General
The ICS1893CF is a low-power, physical-layer device (PHY)
that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection
(CSMA/CD) Ethernet standards, ISO/IEC 8802-3.
The ICS1893CF is intended for MII, Node applications that
require the Auto-MDIX feature that automatically corrects
www.DataSheect4roUs.csoomver errors in plant wiring.
The ICS1893CF incorporates Digital-Signal Processing (DSP)
control in its Physical-Medium Dependent (PMD) sub layer. As
a result, it can transmit and receive data on unshielded
twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100MHz. With this ICS-patented
technology, the ICS1893CF can virtually eliminate errors from
killer packets.
The ICS1893CF provides a Serial-Management Interface for
exchanging command and status information with a
Station-Management (STA) entity. The ICS1893CF
Media-Dependent Interface (MDI) can be configured to
provide either half- or full-duplex operation at data rates of 10
Mb/s or 100Mb/s.
The ICS1893CF is available in a 300-mil 48-lead SSOP
package. The ICS1893CF shares the same proven
performance circuitry with the ICS1893BF and is a pin-for-pin
replacement of the 1893BF.
Applications: NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines, printers,
network connected appliances, and industrial equipment.
Features
Supports category 5 cables with attenuation in excess of
24dB at 100 MHz.
Single-chip, fully integrated PHY provides PCS, PMA, PMD,
and AUTONEG sub layers functions of IEEE standard.
10Base-T and 100Base-TX IEEE 8802.3 compliant
Single 3.3V power supply
Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
– Loopback mode for Diagnostic Functions
– Auto-MDI/MDIX crossover correction
Low-power CMOS (typically 400 mW)
Power-Down mode typically 21mW
Clock and crystal supported
Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
Small footprint 48-pin 300 mil. SSOP package
Also available in small footprint 56-pin 8x8 MLF2 package
Available in Industrial Temp and Lead Free
ICS1893CF Block Diagram
10/100 MII
MAC
Interface
MII
Management
Interface
Interface
MUX
MII
Extended
Register
Set
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
Low-Jitter
Clock
Synthesizer
Clock
100Base-T
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Configuration
and Status
Integrated
Switch
Auto-
Negotiation
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
Power
LEDs and PHY
Address
ICS1893CF, Rev. F, 03/01/07
IDT reserves the right to make changes in the device data identified in
this publication without further notice. IDT advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
Mar. 2007

1 page




ICS1893CF pdf
ICS1893CF Data Sheet Rev. F - Release
Chapter 2 Conventions and Nomenclature
Chapter 2 Conventions and Nomenclature
Table 2-1 lists and explains the conventions and nomenclature used throughout this data sheet.
Table 2-1. Conventions and Nomenclature
Item
Bits
www.DataSheet4U.com
Code groups
Colon (:)
Numbers
Pin (or signal) names
Registers
Convention / Nomenclature
A bit in a register is identified using the format ‘register.bit’. For example, bit
0.15 is bit 15 of register 0.
When a colon is used with bits, it indicates the range of bits. For example,
bits 1.15:11 are bits 15, 14, 13, 12, and 11 of register 1.
For a range of bits, the order is always from the most-significant bit to the
least-significant bit.
Within this table, see the item ‘Symbols’
Within this table, see these items:
‘Bits’
‘Pin (or signal) names’
As a default, all numbers use the decimal system (that is, base 10) unless
followed by a lowercase letter. A string of numbers followed by a lowercase
letter:
– A ‘b’ represents a binary (base 2) number
– An ‘h’ represents a hexadecimal (base 16) number
– An ‘o’ represents an octal (base 8) number
All numerical references to registers use decimal notation (and not
hexadecimal).
All pin or signal names are provided in capital letters.
A pin name that includes a forward slash ‘/’ is a multi-function, configuration
pin. These pins provide the ability to select between two ICS1893CF
functions. The name provided:
– Before the ‘/’ indicates the pin name and function when the signal level
on the pin is logic zero.
– After the ‘/’ indicates the pin name and function when the signal level on
the pin is logic one.
For example, the HW/SW pin selects between Hardware (HW) mode and
Software (SW) mode. When the signal level on the HW/SW pin is logic:
– Zero, the ICS1893CF Hardware mode is selected.
– One, the ICS1893CF Software mode is selected.
An ‘n’ appended to the end of a pin name or signal name (such as
RESETn) indicates an active-low operation.
When a colon is used with pin or signal names, it indicates a range. For
example, TXD[3:0] represents pins/signals TXD3, TXD2, TXD1, and TXD0.
When pin name abbreviations are spelled out, words in parentheses
indicate additional description that is not part of the pin name abbreviation.
A bit in a register is identified using the format ‘register.bit’. For example, bit
0.15 is bit 15 of register 0.
All numerical references to registers use decimal notation (and not
hexadecimal).
When register name abbreviations are spelled out, words in parentheses
indicate additional description that is not part of the register name
abbreviation.
ICS1893CF, Rev. F, 03/01/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
Mar. 2007
5

5 Page





ICS1893CF arduino
ICS1893CF Data Sheet Rev. F - Release
Chapter 4 Operating Modes Overview
4.1.2 Specific Reset Operations
This section discusses the following specific ways that the ICS1893CF can be reset:
Hardware reset (using the RESETn pin)
Power-on reset (applying power to the ICS1893CF)
Software reset (using Control Register bit 0.15)
Note: At the completion of a reset (either hardware, power-on, or software), the ICS1893CF sets all
registers to their default values.
4.1.2.1 Hardware Reset
Entering Hardware Reset
www.DataSheet4U.com Holding the active-low RESETn pin low for a minimum of five REF_IN clock cycles initiates a hardware
reset (that is, the ICS1893CF enters the reset state). During reset, the ICS1893CF executes the steps
listed in Section 4.1.1.1, “Entering Reset”.
Exiting Hardware Reset
After the signal on the RESETn pin transitions from a low to a high state, the ICS1893CF completes in 640
ns (that is, in 16 REF_IN clocks) steps 1 through 5, listed in Section 4.1.1.2, “Exiting Reset”. After the first
five steps are completed, the Serial Management Port is ready for normal operations, but this action does
not signify the end of the reset cycle. The reset cycle completes when the transmit clock (TXCLK) and
receive clock (RXCLK) are available, which is typically 53 ms after the RESETn pin goes high. [For details
on this transition, see Section 9.5.16, “Reset: Hardware Reset and Power-Down”.]
Note:
1. The MAC Interface is not available for use until the TXCLK and RXCLK are valid.
2. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit
that is used to initiate a software reset.
4.1.2.2 Power-On Reset
Entering Power-On Reset
When power is applied to the ICS1893CF, it waits until the potential between VDD and VSS achieves a
minimum voltage before entering reset and executing the steps listed in Section 4.1.1.1, “Entering Reset”.
After entering reset from a power-on condition, the ICS1893CF remains in reset for approximately 20 µs.
(For details on this transition, see Section 9.5.15, “Reset: Power-On Reset”.)
Exiting Power-On Reset
The ICS1893CF automatically exits reset and performs the same steps as for a hardware reset. (See
Section 4.1.1.2, “Exiting Reset”.)
Note: The only difference between a hardware reset and a power-on reset is that during a power-on
reset, the ICS1893CF isolates its RESETn input pin. All other functionality is the same. As with a
hardware reset, Control Register bit 0.15 does not represent the status of a power-on reset.
ICS1893CF, Rev. F, 03/01/07
Copyright © 2007, Integrated Device Technology, Inc.
All rights reserved.
11
Mar. 2007

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