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PDF ICS1893BF Data sheet ( Hoja de datos )
| Número de pieza | ICS1893BF | |
| Descripción | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM | |
| Fabricantes | Integrated Circuit Systems | |
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Integrated Circuit Systems, Inc.
ICS1893BF
Document Type: Data Sheet
Document Stage: Rev. C Release
3.3-V 10Base-T/100Base-TX Integrated PHYceiver™
General
The ICS1893BF is a low-power, physical-layer device (PHY)
that supports the ISO/IEC 10Base-T and 100Base-TX
Carrier-Sense Multiple Access/Collision Detection
(CSMA/CD) Ethernet standards, ISO/IEC 8802-3.
The ICS1893BF is intended for MII, Node applications that
require the Auto-MDIX feature that automatically corrects
www.DataSheect4roUs.csoomver errors in plant wiring.
The ICS1893BF incorporates Digital-Signal Processing (DSP)
control in its Physical-Medium Dependent (PMD) sub layer. As
a result, it can transmit and receive data on unshielded
twisted-pair (UTP) category 5 cables with attenuation in
excess of 24 dB at 100MHz. With this ICS-patented
technology, the ICS1893BF can virtually eliminate errors from
killer packets.
The ICS1893BF provides a Serial-Management Interface for
exchanging command and status information with a
Station-Management (STA) entity. The ICS1893BF
Media-Dependent Interface (MDI) can be configured to
provide either half- or full-duplex operation at data rates of 10
Mb/s or 100Mb/s.
The ICS1893BF is available in a 300-mil 48-lead SSOP
package. The ICS1893BF shares the same proven
performance circuitry with the ICS1893AF but is not a
pin-for-pin replacement of the 1893AF. An application note for
a dual footprint layout to accommodate ICS1893AF or
ICS1893BF is available on the ICS website.
Applications: NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines,
printers.
Features
• Supports category 5 cables with attenuation in excess of
24dB at 100 MHz.
• Single-chip, fully integrated PHY provides PCS, PMA, PMD,
and AUTONEG sub layers functions of IEEE standard.
• 10Base-T and 100Base-TX IEEE 8802.3 compliant
• Single 3.3V power supply
• Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full and half-duplex modes
– Loopback mode for Diagnostic Functions
– Auto-MDI/MDIX crossover correction
• Low-power CMOS (typically 400 mW)
• Power-Down mode typically 21mW
• Clock and crystal supported
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander correction
– Transmit wave shaping and stream cipher scrambler
– MLT-3 encoder and NRZ/NRZI encoder
• Small footprint 48-pin 300 mil. SSOP package
• Also available in small footprint 56-pin 8x8 MLF2 package
• Available in Industrial Temp and Lead Free
ICS1893BF Block Diagram
10/100 MII
MAC
Interface
MII
Management
Interface
Interface
MUX
MII
Extended
Register
Set
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
Low-Jitter
Clock
Synthesizer
Clock
100Base-T
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
10Base-T
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Configuration
and Status
Integrated
Switch
Auto-
Negotiation
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
Power
LEDs and PHY
Address
ICS1893BF, Rev. C, 9/29/05
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any information
being relied upon by the customer is current and accurate.
September, 2005
1 page  
ICS1893BF Data Sheet Rev. C - Release
Table of Contents
Table of Contents
Section
7.5
7.5.1
7.5.2
7.5.3
7.6
www.DataSheet4U.com 7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.8
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.9.5
7.9.6
7.10
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
Title
Page
Register 3: PHY Identifier Register ........................................................................ 63
OUI bits 19-24 (bits 3.15:10) .................................................................................. 63
Manufacturer's Model Number (bits 3.9:4) ............................................................. 63
Revision Number (bits 3.3:0) ................................................................................. 63
Register 4: Auto-Negotiation Register ................................................................... 65
Next Page (bit 4.15) ............................................................................................... 65
IEEE Reserved Bit (bit 4.14) .................................................................................. 66
Remote Fault (bit 4.13) .......................................................................................... 66
IEEE Reserved Bits (bits 4.12:10) ......................................................................... 66
Technology Ability Field (bits 4.9:5) ....................................................................... 67
Selector Field (Bits 4.4:0) ....................................................................................... 67
Register 5: Auto-Negotiation Link Partner Ability Register .................................... 68
Next Page (bit 5.15) ............................................................................................... 68
Acknowledge (bit 5.14) .......................................................................................... 69
Remote Fault (bit 5.13) .......................................................................................... 69
Technology Ability Field (bits 5.12:5) ..................................................................... 69
Selector Field (bits 5.4:0) ....................................................................................... 69
Register 6: Auto-Negotiation Expansion Register .................................................. 70
IEEE Reserved Bits (bits 6.15:5) ........................................................................... 70
Parallel Detection Fault (bit 6.4) ............................................................................. 71
Link Partner Next Page Able (bit 6.3) .................................................................... 71
Next Page Able (bit 6.2) ......................................................................................... 71
Page Received (bit 6.1) ......................................................................................... 71
Link Partner Auto-Negotiation Able (bit 6.0) .......................................................... 71
Register 7: Auto-Negotiation Next Page Transmit Register ................................... 72
Next Page (bit 7.15) ............................................................................................... 73
IEEE Reserved Bit (bit 7.14) .................................................................................. 73
Message Page (bit 7.13) ........................................................................................ 73
Acknowledge 2 (bit 7.12) ....................................................................................... 73
Toggle (bit 7.11) ..................................................................................................... 73
Message Code Field / Unformatted Code Field (bits 7.10:0) ................................. 73
Register 8: Auto-Negotiation Next Page Link Partner Ability Register ................... 74
Next Page (bit 8.15) ............................................................................................... 75
IEEE Reserved Bit (bit 8.14) .................................................................................. 75
Message Page (bit 8.13) ........................................................................................ 75
Acknowledge 2 (bit 8.12) ....................................................................................... 75
Message Code Field / Unformatted Code Field (bits 8.10:0) ................................. 75
ICS1893BF, Rev. C, 9/29/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
5
September, 2005
5 Page 
ICS1893BF Data Sheet Rev. C - Release
Chapter 1 Abbreviations and Acronyms
Table 1-1. Abbreviations and Acronyms (Continued)
Abbreviation /
Acronym
Interpretation
OSI Open Systems Interconnection
OUI Organizationally Unique Identifier
PCS
PHY
Physical Coding sublayer
physical-layer device
The ICS1893BF is a physical-layer device, also referred to as a ‘PHY’ or ‘PHYceiver’.
(The ICS1890 is also a physical-layer device.)
PLL
www.DataSheet4U.com PMA
phase-locked loop
Physical Medium Attachment
PMD
ppm
Physical Medium Dependent
parts per million
RO read only
R/W read/write
R/W0
SC
read/write zero
self-clearing
SF
SFD
Special Functions
Start-of-Frame Delimiter
SI Stream Interface, Serial Interface, or Symbol Interface.
With reference to the MII/SI pin, the acronym ‘SI’ has multiple meanings.
• Generically, SI means 'Stream Interface', and is documented as such in this data
sheet.
• However, when the MAC Interface is configured for:
– 10M operations, SI is an acronym for 'Serial Interface'.
– 100M operations, SI is an acronym for 'Symbol Interface'.
SQE
SSD
Signal Quality Error
Start-of-Stream Delimiter
SSOP
STA
Small Shrink Outline Package
Station Management Entity
STP
TAF
shielded twisted pair
Technology Ability Field
TP-PMD
Typ.
Twisted-Pair Physical Layer Medium Dependent
typical
UTP
unshielded twisted pair
ICS1893BF, Rev. C, 9/29/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
11
September, 2005
11 Page | ||
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