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PDF FM31L274 Datasheet ( Hoja de datos )

Número de pieza FM31L274
Descripción (FM31L27x) 3V Integrated Processor Companion
Fabricantes Ramtron 
Logotipo Ramtron Logotipo

Total 25 Páginas
		
FM31L274 Hoja de datos, Descripción, Manual
Pre-Production
FM31L278/L276/L274/L272
3V Integrated Processor Companion with Memory
Features
High Integration Device Replaces Multiple Parts
Serial Nonvolatile Memory
Real-time Clock (RTC)
Low Voltage Reset
Watchdog Timer
Early Power-Fail Warning/NMI
Two 16-bit Event Counters
Serial Number with Write-lock for Security
www.DataSheet4U.cFoemrroelectric Nonvolatile RAM
4Kb, 16Kb, 64Kb, and 256Kb versions
Unlimited Read/Write Endurance
10 year Data Retention
NoDelay™ Writes
Processor Companion
Active-low Reset Output for VDD and Watchdog
Programmable VDD Reset Trip Point
Manual Reset Filtered and Debounced
Programmable Watchdog Timer
Dual Battery-backed Event Counter Tracks
System Intrusions or other Events
Comparator for Early Power-Fail Interrupt
64-bit Programmable Serial Number with Lock
Fast Two-wire Serial Interface
Up to 1 MHz Maximum Bus Frequency
Supports Legacy Timing for 100 kHz & 400 kHz
Device Select Pins for up to 4 Memory Devices
RTC, Supervisor Controlled via 2-wire Interface
Real-time Clock/Calendar
Backup Current under 1 µA
Seconds through Centuries in BCD format
Tracks Leap Years through 2099
Uses Standard 32.768 kHz Crystal (12.5pF)
Software Calibration
Supports Battery or Capacitor Backup
Description
The FM31L27x is a family of integrated devices that
includes the most commonly needed functions for
processor-based systems. Major features include
nonvolatile memory available in various sizes, real-
time clock, low-VDD reset, watchdog timer,
nonvolatile event counter, lockable 64-bit serial
number area, and general purpose comparator that
can be used for an early power-fail (NMI) interrupt or
other purpose. The family operates from 2.7 to 3.6V.
Each FM31L27x provides nonvolatile RAM
available in sizes including 4Kb, 16Kb, 64Kb, and
256Kb versions. Fast write speed and unlimited
endurance allow the memory to serve as extra RAM
or conventional nonvolatile storage. This memory is
truly nonvolatile rather than battery backed.
The real-time clock (RTC) provides time and date
information in BCD format. It can be permanently
powered from external backup voltage source, either
a battery or a capacitor. The timekeeper uses a
common external 32.768 kHz crystal and provides a
calibration mode that allows software adjustment of
timekeeping accuracy.
Easy to Use Configurations
Operates from 2.7 to 3.6V
14-pin “Green”/RoHS SOIC package (-G)
Low Operating Current
-40°C to +85°C Operation
The processor companion includes commonly needed
CPU support functions. Supervisory functions
include a reset output signal controlled by either a
low VDD condition or a watchdog timeout. /RST
goes active when VDD drops below a programmable
threshold and remains active for 100 ms after VDD
rises above the trip point. A programmable watchdog
timer runs from 100 ms to 3 seconds. The watchdog
timer is optional, but if enabled it will assert the reset
signal for 100 ms if not restarted by the host before
the timeout. A flag-bit indicates the source of the
reset.
A general-purpose comparator compares an external
input pin to the onboard 1.2V reference. This is
useful for generating a power-fail interrupt (NMI) but
can be used for any purpose. The family also includes
a programmable 64-bit serial number that can be
locked making it unalterable. Additionally it offers a
dual battery-backed event counter that tracks the
number of rising or falling edges detected on
dedicated input pins.
This is a product in pre-production phase of development. Device
characterization is complete and Ramtron does not expect to change
the specifications. Ramtron will issue a Product Change Notice if
any specification changes are made.
Rev. 2.0
Dec. 2007
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
Page 1 of 25

1 page

FM31L274 pdf
VTP
2.6V
2.9V
VTP
0
1
The watchdog timer can also be used to assert the
reset signal (/RST). The watchdog is a free running
programmable timer. The period can be software
programmed from 100 ms to 3 seconds in 100 ms
increments via a 5-bit nonvolatile register. All
programmed settings are minimum values and vary
with temperature according to the operating
specifications. The watchdog has two additional
controls associated with its operation, a watchdog
enable bit (WDE) and timer restart bits (WR). Both
www.DataSheet4U.cttohimme eeonuatbilne
bit must be
order to drive
set and the watchdog
/RST active. If a reset
must
event
occurs, the timer will automatically restart on the
rising edge of the reset pulse. If WDE=0, the
watchdog timer runs but a watchdog fault will not
cause /RST to be asserted low. The WTR flag will be
set, indicating a watchdog fault. This setting is useful
during software development and the developer does
not want /RST to drive. Note that setting the
maximum timeout setting (11111b) disables the
counter to save power. The second control is a nibble
that restarts the timer preventing a reset. The timer
should be restarted after changing the timeout value.
The watchdog timeout value is located in register
0Ah, bits 4-0, and the watchdog enable is bit 7. The
watchdog is restarted by writing the pattern 1010b to
the lower nibble of register 09h. Writing this pattern
will also cause the timer to load new timeout values.
Writing other patterns to this address will not affect
its operation. Note the watchdog timer is free-
running. Prior to enabling it, users should restart the
timer as described above. This assures that the full
timeout period will be set immediately after enabling.
The watchdog is disabled when VDD is below VTP.
The following table summarizes the watchdog bits. A
block diagram follows.
Watchdog timeout
Watchdog enable
Watchdog restart
WDT4-0
WDE
WR3-0
0Ah, bits 4-0
0Ah, bit 7
09h, bits 3-0
100 ms
clock
Timebase
WR3-0 = 1010b to restart
Counter
/RST
Watchdog
timeout
WDE
Figure 3. Watchdog Timer
Rev. 2.0
Dec. 2007
FM31L278/L276/L274/L272 - 3V I2C Companion
Manual Reset
The /RST pin is bi-directional and allows the
FM31L27x to filter and de-bounce a manual reset
switch. The /RST input detects an external low
condition and responds by driving the /RST signal
low for 100 ms.
MCU
RST
Reset
Switch
FM31L27x
Switch
Behavior
RST
FM31L27x
drives
100 ms (min.)
Figure 4. Manual Reset
Note that an internal weak pull-up on /RST
eliminates the need for additional external
components.
Reset Flags
In case of a reset condition, a flag will be set to
indicate the source of the reset. A low VDD reset or
manual reset is indicated by the POR flag, register
09h bit 6. A watchdog reset is indicated by the WTR
flag, register 09h bit 7. Note that the flags are
internally set in response to reset sources, but they
must be cleared by the user. When the register is
read, it is possible that both flags are set if both have
occurred since the user last cleared them.
Early Power Fail Comparator
An early power fail warning can be provided to the
processor well before VDD drops out of spec. The
comparator is used to create a power fail interrupt
(NMI). This can be accomplished by connecting the
PFI pin to the unregulated power supply via a resistor
divider. An application circuit is shown below.
Regulator
VDD
FM31L27x
To MCU CAL/PFO
NMI input
+
- 1.2V ref
PFI
Figure 5. Comparator as Early Power-Fail Warning
Page 5 of 25

5 Page

FM31L274 arduino
FM31L278/L276/L274/L272 - 3V I2C Companion
Register Description
Address Description
18h
17h
16h
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15h
14h
13h
12h
11h
10h
0Fh
0Eh
0Dh
Serial Number Byte 7
D7 D6 D5 D4 D3 D2 D1 D0
SN.63
SN.62
SN.61
SN.60
SN.59
SN.58
SN.57
Upper byte of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Serial Number Byte 6
D7 D6 D5 D4 D3 D2 D1
SN.56
D0
SN.55
SN.54
SN.53
SN.52
SN.51
SN.50
SN.49
Byte 6 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Serial Number Byte 5
D7 D6 D5 D4 D3 D2 D1
SN.48
D0
SN.47
SN.46
SN.45
SN.44
SN.43
SN.42
SN.41
Byte 5 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Serial Number Byte 4
D7 D6 D5 D4 D3 D2 D1
SN.40
D0
SN.39
SN.38
SN.37
SN.36
SN.35
SN.34
SN.33
Byte 4 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Serial Number Byte 3
D7 D6 D5 D4 D3 D2 D1
SN.32
D0
SN.31
SN.30
SN.29
SN.28
SN.27
SN.26
SN.25
Byte 3 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Serial Number Byte 2
D7 D6 D5 D4 D3 D2 D1
SN.24
D0
SN.23
SN.22
SN.21
SN.20
SN.19
SN.18
SN.17
Byte 2 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Serial Number Byte 1
D7 D6 D5 D4 D3 D2 D1
SN.16
D0
SN.15
SN.14
SN.13
SN.12
SN.11
SN.10
SN.9
Byte 1 of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Serial Number Byte 0
D7 D6 D5 D4 D3 D2 D1
SN.8
D0
SN.7
SN.6
SN.5
SN.4
SN.3
SN.2
SN.1
LSB of the serial number. Read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Counter 2 MSB
D7 D6 D5 D4 D3 D2 D1
SN.0
D0
C2.15
C2.14
C2.13
C2.12
C2.11
C2.10
C2.9
Event Counter 2 MSB. Increments on overflows from Counter 2 LSB. Battery-backed, read/write.
Counter 2 LSB
D7 D6 D5 D4 D3 D2 D1
C2.8
D0
C2.7 C2.6 C2.5 C2.4 C2.3 C2.2 C2.1 C2.0
Event Counter 2 LSB. Increments on programmed edge event on CNT2 input or overflows from Counter 1 MSB
when CC=1. Battery-backed, read/write .
Counter 1 MSB
D7 D6 D5 D4 D3 D2 D1 D0
C1.15
C1.14
C1.13
C1.12
C1.11
C1.10
C1.9
Event Counter 1 MSB. Increments on overflows from Counter 1 LSB. Battery-backed, read/write.
Counter 1 LSB
D7 D6 D5 D4 D3 D2 D1
C1.8
D0
C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0
Event Counter 1 LSB. Increments on programmed edge event on CNT1 input. Battery-backed, read/write.
Rev. 2.0
Dec. 2007
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