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PDF EP9132 Data sheet ( Hoja de datos )

Número de pieza EP9132
Descripción HDMI 1.3 Splitter
Fabricantes PCA Electronics 
Logotipo PCA Electronics Logotipo



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No Preview Available ! EP9132 Hoja de datos, Descripción, Manual

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HDMI 1.3 Splitter
EP9132
User Guide — EP9132_UG V0.1
User Guide
V0.1
Revised Date: Jan. 04, 2008
Original Release Date: Apr. 19, 2007
Explore
Explore reserves the right to make changes without further notice to any products herein to improve reliability, function or design.
Explore does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it
convey any license under its patent rights nor the rights of others. Explore products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for
any other application in which the failure of the Explore product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Explore products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Explore and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses,
and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended
or unauthorized use, even if such claim alleges that Explore was negligent regarding the design or manufacture of the part.
Explore Confidential Proprietary
NON-DISCLOSURE AGREEMENT REQUIRED
1

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EP9132 pdf
Section 2 Overview
2.1 Block Diagram
Figure 2-1 Block Diagram
User Guide — EP9132_UG V0.1
SDA3
SCL3
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EXT_RSTb
EXT_SWING
SDA1
SCL1
SDA2
SCL2
IIC Slave
Registers
&
Logics
IIC Slave
IIC Master
DVI/HDMI
Receiver
HDCP Keys
DVI/HDMI
Transmitter
HDCP Keys
HDCP Keys
DVI/HDMI
Transmitter
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NON-DISCLOSURE AGREEMENT REQUIRED
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EP9132 arduino
User Guide — EP9132_UG V0.1
THSC Link Disabled (Tx power down) to LINK_ON Low4
250
TFSC Link Enabled (DE Active) to LINK_ON High1
25 40
NOTES:
1. Guaranteed by design.
2. Jitter defines as per DVI 1.0 Specification, Section 4.6 Jitter Specification.
3. Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electronical Measurement Procedures
4. Measured when transmitter was powered down.
ms
DE
edges
Transmitter AC Specifications (under normal operating conditions unless otherwise specified)
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Symbol
Parameter
SLHT Differential Swing Low-to-High Transition Time
SHLT Differential Swing High-to-Low Transition Time
Conditions
CLOAD = 5pF,
RLOAD = 50 ohm,
REXT_SWING = 300 ohm
CLOAD = 5pF,
RLOAD = 50 ohm,
REXT_SWING = 300 ohm
Min Typ
Max Units
170 200
230
ps
170 200
230
ps
2 Jitter can be estimated by 1) triggering a digital scope at the rising of input clock and 2) measuring the peak to peak time spread
of the rising edge of the input clock at both 0.5us and 1.0us after the trigger.
3 Actual jitter tolerance may be higher depending on the frequency of the jitter.
Figure 2-3 Differential Output Timing Definition
AVCC
VOD = ABS{(TX+) - (TX-)}
80% VOD
50ohm
TX+
20% VOD
TX-
5pF
SLHT
SHLT
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NON-DISCLOSURE AGREEMENT REQUIRED
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