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PDF CAT28WC129 Data sheet ( Hoja de datos )
| Número de pieza | CAT28WC129 | |
| Descripción | 128K-Bit I2C Serial CMOS E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Preliminary
CAT24WC129
128K-Bit I2C Serial CMOS E2PROM
FEATURES
s 1MHz I2C Bus Compatible*
s 1.8 to 6 Volt Operation
s Low Power CMOS Technology
s 64-Byte Page Write Buffer
www.DataSheet4sU.cSomelf-Timed Write Cycle with Auto-Clear
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24WC129 is a 128K-bit Serial CMOS E2PROM
internally organized as 16384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
s Write Protect Feature
– Top 1/4 Array Protected When WP at VIH
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-Pin DIP or 8-Pin SOIC
CAT24WC129 features a 64-byte page write buffer. The
device operates via the I2C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J,K)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
24WC129 F01
PIN FUNCTIONS
Pin Name
Function
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6V Power Supply
VSS Ground
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
XDEC 256
E2PROM
256X512
CONTROL
WP LOGIC
SCL STATE COUNTERS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
24WC129 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25065-00 6/99 S-1
1 page  
Preliminary
CAT24WC129
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The seven most
significant bits of the 8-bit slave address are fixed as
1010XXX (Fig. 5), where X can be a 0 or 1. The last bit
of the slave address specifies whether a Read or Write
operation is to be performed. When this bit is set to 1, a
Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC129 monitors the bus and
www.DataSheet4rUe.scpomonds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC129 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC129 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24WC129 begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
Figure 4. Acknowledge Timing
knowledge, the CAT24WC129 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC129. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC129 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, the device will not respond to any request from
the Master device.
Page Write
The CAT24WC129 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24WC129 will respond with an
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1 0 1 0 AX2 AX1 AX0 R/W
X is Don't Care, can be a '0' or a '1'.
5020 FHD F06
5027 FHD F07
5 Doc. No. 25065-00 6/99 S-1
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CAT28WC129.PDF ] | |
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