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PDF L6591 Data sheet ( Hoja de datos )

Número de pieza L6591
Descripción PWM controller
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! L6591 Hoja de datos, Descripción, Manual

L6591
PWM controller for ZVS half-bridge
Features
Complementary PWM control for soft-switched
www.DataSheet4U.comhalf-bridge with programmable dead-time
Up to 500 kHz operating frequency
On-board high-voltage start-up
Advanced light load management
Adaptive UVLO
Pulse-by-pulse OCP
OLP (latched or autorestart)
Transformer saturation detection
Interface with PFC controller
Latched disable input
Input for power-on sequencing or brownout
protection
Programmable soft-start
4 % precision external reference
Figure 1. Typical application circuit
SO16 narrow
SO-16
600 V-rail compatible high-side gate driver with
integrated bootstrap diode and high dV/dt
immunity
SO16N package
Applications
High power AC-DC adapter/charger
Desktop PC, entry-level server
Telecom SMPS
5
OSC
TIMING
HV
16
CLK
V CC
9
25 V
HV ge nerator ON/O FFa nd
a daptive UV LOmanag ement
VREG
Vre f
2
DIS
4.5V
+
-
R
SQ
1.5V
ISEN
3
PFC_STOP
8
1
LINE
1 5µA
HICCUP
-
+
OCP2
DI S
1.5V
-
+
BLANKI NG
R
Q
S
+
PWM
-
OCP2
Ilimre f
0 .8 V max.
LI NE_OK
+
OCP
-
SOFT-START
4
Low
UVLO
Vcc_OK
DIS
SQ
R
P WM _CT L
Vc c_O K
DIS
S HUT DO WN
LI NE_ OK
BURST- M ODE CTRL
+
-
1.7 5V
3R
R
VREG
0.3 2mA
-
+
2.0 V
7
SS COMP
6
VREF
Sync hronou s
bo otstra p diode
15
BOOT
L EVEL
SHIFTER
V CC
14
HVG
13
FGND
L ow
UV LO
10
LV G
11
GND
June 2008
Rev 1
1/32
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32

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L6591 pdf
L6591
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Pin settings
Table 1. Pin functions (continued)
Pin N.
Name
Function
Current sense (PWM comparator) input. The voltage on this pin is internally
compared with an internal reference derived from the voltage on pin COMP
and when they are equal the high-side gate drive output (previously
asserted high by the clock signal generated by the oscillator) is driven low to
turn off the upper power MOSFET; the lower MOSFET is turned on after a
delay programmed by the timing capacitor at pin OSC (#5). The pin is
3 ISEN equipped with 200 ns blanking time for improved noise immunity. A second
comparator referenced at 0.8 V turns off the upper MOSFET if the voltage
at the pin exceeds the threshold, overriding the PWM comparator (pulse-by-
pulse OCP). A third comparison level located at 1.5 V shuts the device
down and brings its consumption almost to a “before start-up” level (hiccup-
mode OCP) to prevent uncontrolled current rise. A logic circuit improves
sensitivity to temporary disturbances.
Soft-start. An internal 20 µA generator charges an external capacitor
connected between the pin and GND (#11) generating a voltage ramp.
During the ramp, the internal reference for pulse-by-pulse OCP (see pin #3,
ISEN) rises linearly starting from zero to its final value, thus causing the
4 SS duty cycle of the upper MOSFET to rise starting from zero as well, and all
the functions monitoring pin COMP (#7) are disabled. The same capacitor
is used to delay IC’s shutdown (latch-off or auto-restart mode selectable)
after detecting an overcurrent condition. The SS capacitor is quickly
discharged as the chip goes into UVLO.
Oscillator pin. A resistor to VREF (#6) and a capacitor from the pin to GND
(#11) define the oscillator frequency. The maximum duty cycle is limited
5
OSC
below 50 % by an internal T-flip-flop. As a result, the switching frequency will
be half that of the oscillator. The capacitor value defines the dead-time
separating the conduction state of either MOSFET. This capacitor should
not be lower than 220 pF.
Voltage reference. An internal generator furnishes an accurate voltage
reference (5 V±4 %, all inclusive) that can be used to supply up to 5 mA to
6 VREF an external circuit. A small film capacitor (0.1 µF typ.), connected between
this pin and GND (#11) is recommended to ensure the stability of the
generator and to prevent noise from affecting the reference.
Control input for PWM regulation. The pin is to be driven by the
phototransistor (emitter-grounded) of an octocoupler to modulate the
voltage by modulating the current sunk from (sourced by) the pin (0.4 mA
typ.). It is recommended to place a small filter capacitor between the pin
7 COMP and GND (#11), as close to the IC as possible to reduce switching noise
pick up, to set a pole in the output-to-control transfer function. A voltage
lower than 1.75 V shuts down the IC and reduces its current consumption.
The chip restarts as the voltage exceeds 1.8 V. This function realizes burst-
mode operation at light load.
Open-drain ON/OFF control of PFC controller. This pin is intended for
temporarily stopping the PFC controller at light load in systems comprising
a PFC pre-regulator, during burst-mode operation (see pin COMP, #7). The
8
PFC_STOP
pin, normally open, goes low if the voltage on COMP is lower than 1.75 V
and opens when the voltage on pin COMP exceeds 1.8V. Whenever the IC
is shut down (SS > 5 V, DIS>4.5, ISEN >1.5 V) the pin is low as well,
provided the supply voltage of the IC is above the restart threshold (typ. 5
V). It is open during UVLO. Leave the pin open if not used
5/32

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L6591 arduino
L6591
www.DataSheet4U.com
Electrical characteristics
Table 4.
Symbol
Electrical characteristics (continued)
(TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 12 V, CHVG = CLVG = 1 nF; RT = 22 k,
CT = 330 pF; unless otherwise specified)
Parameter
Test condition
Min Typ Max Unit
tr Rise time
UVLO saturation
Vcc = 0 to VccOn,
Isink = 1 mA
High-side gate driver (voltages referred to FGND)
80 ns
1.1 V
VHVGL Output low voltage
VHVGH
Isourcepk
Isinkpk
Output high voltage
Peak source current (3)
Peak sink current (3)
tf Fall time
tr Rise time
Pull-down resistor
Isink = 200 mA
Isource = 5 mA
1.5 V
11 11.9
V
-0.3 A
0.8 A
40 ns
80 ns
25 k
1. Parameters in tracking each other
2. Parameters in tracking each other
3. Parameters guaranteed by design
11/32

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