|
|
PDF LH28F128BFHED-PWTLZ8 Data sheet ( Hoja de datos )
| Número de pieza | LH28F128BFHED-PWTLZ8 | |
| Descripción | Flash Memory | |
| Fabricantes | Sharp | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LH28F128BFHED-PWTLZ8 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
PRODUCT SPECIFICATION
Integrated Circuits Group
www.DataSheet4U.com
LH28F128BFHED-PWTLZ8
Flash Memory
128Mbit (8Mbitx16)
(Model Number: LHF12FZ8)
Spec. Issue Date: October 26, 2004
Spec No: EL16X218
1 page  
LHF12FZ8
2
LH28F128BFHED-PWTLZ8
128Mbit (8Mbit×16)
Page Mode Dual Work Flash MEMORY
128M density with 16Bit I/O Interface
• 2 Bank Enable (BE0#, BE1#) Control
High Performance Reads
• 90/35ns 8-Word Page Mode
Configurative 8-Plane Dual Work
www.DataSheet4•UF.cloemxible Partitioning
• Read operations during Block Erase or (Page Buffer)
Program
• Status Register for Each Partition
Low Power Operation
• 2.7V Read and Write Operations
• Automatic Power Savings Mode Reduces ICCR
in Static Mode
Enhanced Code + Data Storage
• 5µs Typical Erase/Program Suspends
OTP (One Time Program) Block
• 4-Word Factory-Programmed Area
• 4-Word User-Programmable Area
High Performance Program with Page Buffer
• 16-Word Page Buffer
• 5µs/Word (Typ.) at 12V VPP
Operating Temperature -40°C to +85°C
CMOS Process (P-type silicon substrate)
Flexible Blocking Architecture
• Sixteen 4K-word Parameter Blocks
• Two-hundred and fifty-four 32K-word Main Blocks
• Top and Bottom Parameter Location
Enhanced Data Protection Features
• Individual Block Lock and Block Lock-Down with
Zero-Latency
• All blocks are locked at power-up or device reset.
• Absolute Protection with VPP≤VPPLK
• Block Erase, Bank Erase, (Page Buffer) Word
Program Lockout during Power Transitions
Automated Erase/Program Algorithms
• 3.0V Low-Power 11µs/Word (Typ.)
Programming
• 12V No Glue Logic 9µs/Word (Typ.)
Production Programming and 0.5s Erase (Typ.)
Cross-Compatible Command Support
• Basic Command Set
• Common Flash Interface (CFI)
Extended Cycling Capability
• Minimum 100,000 Block Erase Cycles
48-Lead TSOP
ETOXTM* Flash Technology
Not designed or rated as radiation hardened
The product, which is 8-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash memory, is a low
power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can
operate at VCC=2.7V-3.6V and VPP=1.65V-3.6V or 11.7V-12.3V. Its low voltage operation capability greatly extends
battery life for portable applications.
The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus
eliminating time consuming wait states. Furthermore, its newly configurative partitioning architecture allows flexible dual
work operation.
The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main
Blocks that provide maximum flexibility for safe nonvolatile code and data storage.
Fast program capability is provided through the use of high speed Page Buffer Program.
Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.
* ETOX is a trademark of Intel Corporation.
Rev. 2.44
5 Page 
LHF12FZ8
8
Table 3. Identifier Codes and OTP Address for Read Operation
Code
Address
[A15-A0]
Data
[DQ15-DQ0]
Manufacturer Code
Device Code
Manufacturer Code
Device Code
Block Lock Configuration
Code
www.DataSheet4U.com
Device Configuration Code
OTP
Block is Unlocked
Block is Locked
Block is not Locked-Down
Block is Locked-Down
Partition Configuration Register
OTP Lock
OTP
0000H
0001H
Block
Address
+2
0006H
0080H
0081-0088H
00B0H
00B0H (BE0#=VIL)
00B1H (BE1#=VIL)
DQ0 = 0
DQ0 = 1
DQ1 = 0
DQ1 = 1
PCRC
OTP-LK
OTP
NOTES:
1. The address A21-A16 are shown in below table for reading the manufacturer code, device code,
device configuration code and OTP data.
2. Bank 0 (selected by BE0#=VIL) has its parameter blocks in the plane3 (The highest address within the bank).
Bank 1 (selected by BE1#=VIL) has its parameter blocks in the plane0 (The lowest address within the bank).
3. Block Address = The beginning location of a block address within the partition to which
the Read Identifier Codes/OTP command (90H) has been written.
DQ15-DQ2 are reserved for future implementation.
4. PCRC=Partition Configuration Register Code.
5. OTP-LK=OTP Block Lock configuration.
6. OTP=OTP Block data.
7. When the data within OTP block is read, BE0# must be VIL.
OTP block in Bank 1 (selected by BE1#=VIL) should not be used.
Notes
1
1, 2
3
3
3
3
1, 4
1, 5, 7
1, 6, 7
Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration(1)
Partition Configuration Register (2)
Address(3)
PCR.10
PCR.9
PCR.8
[A21-A16]
0 0 0 00H
0 0 1 00H or 10H
0 1 0 00H or 20H
1 0 0 00H or 30H
0 1 1 00H or 10H or 20H
1 1 0 00H or 20H or 30H
1 0 1 00H or 10H or 30H
1 1 1 00H or 10H or 20H or 30H
NOTES:
1. The address to read the identifier codes or OTP data is dependent on the partition which is selected
when writing the Read Identifier Codes/OTP command (90H).
2. Refer to Table 12 for the partition configuration register.
3. When the data within OTP block is read, BE0# must be VIL.
OTP block in Bank 1 (selected by BE1#=VIL) should not be used.
Rev. 2.44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LH28F128BFHED-PWTLZ8.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LH28F128BFHED-PWTLZ8 | Flash Memory | Sharp |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |