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PDF A29L004A Data sheet ( Hoja de datos )

Número de pieza A29L004A
Descripción Boot Sector Flash Memory
Fabricantes AMIC Technology 
Logotipo AMIC Technology Logotipo



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Preliminary
A29L004A Series
512K X 8 Bit CMOS 3.0 Volt-only,
Boot Sector Flash Memory
Document Title
512K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
www.DataShReeetv4Uis.cioomn History
Rev. History
0.0 Initial issue
Issue Date
March 9, 2005
Remark
Preliminary
PRELIMINARY (March, 2005, Version 0.0)
AMIC Technology, Corp.

1 page




A29L004A pdf
A29L004A Series
Absolute Maximum Ratings*
Storage Temperature Plastic Packages . …… .0°C to + 70°C
Ambient Temperature with Power Applied…… 0°C to + 70°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . …... . . . -0.5V to +4.0V
A9, OE & RESET (Note 2) . . . . . . . . . . ….. . -0.5 to +12.5V
All other pins (Note 1) . . . . . . . . . . . ….. -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . ….. … 200mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
www.DataSheett4oU-.2co.0mV for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. During voltage
transitions, input or I/O pins may overshoot to VCC +2.0V
for periods up to 20ns.
2. Minimum DC input voltage on A9, OE and RESET is -
0.5V. During voltage transitions, A9, OE and RESET
may overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may
overshoot to 14.0V for periods up to 20ns. ( RESET is
N/A on 32-pin PLCC & (s)TSOP)
3. No more than one output is shorted at a time. Duration of
the short circuit should not be greater than one second.
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended periods
may affect device reliability.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . ….. . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . ….. . . +2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself does
not occupy any addressable memory location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to the
internal state machine. The state machine outputs dictate the
function of the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29L004A Device Bus Operations
Operation
CE OE
Read
Write
CMOS Standby
Output Disable
Hardware Reset
Sector Protect
(See Note 2)
Sector Unprotect
(See Note 2)
Temporary Sector
Unprotect
L
L
VCC ± 0.3 V
L
X
L
L
X
L
H
X
H
X
H
H
X
WE RESET
A0 – A18
(N/A 32-pin PLCC, (s)TSOP)
HH
AIN
LH
AIN
X VCC ± 0.3 V
X
HH
X
XL
X
L VID Sector Address,
A6=L, A1=H, A0=L
L VID Sector Address,
A6=H, A1=H, A0=L
X VID
AIN
I/O0 - I/O7
DOUT
DIN
High-Z
High-Z
High-Z
DIN
DIN
DIN
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Notes:
1. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.
2. This function is not available on 32-pin PLCC & (s)TSOP packages.
PRELIMINARY (March, 2005, Version 0.0)
4
AMIC Technology, Corp.

5 Page





A29L004A arduino
A29L004A Series
Command Definitions
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing incorrect address and data
values or writing them in the improper sequence resets the
device to reading array data.
All addresses are latched on the falling edge of WE or CE ,
whichever happens later. All data is latched on the rising
edge of WE or CE , whichever happens first. Refer to the
appropriate timing diagrams in the "AC Characteristics"
www.DataShseeectt4ioUn.c. om
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm. After the device accepts an Erase Suspend
command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended
sectors, the device outputs status data. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See "Erase Suspend/Erase Resume Commands"
for more information on this mode.
The system must issue the reset command to re-enable the
device for reading array data if I/O5 goes high, or while in the
autoselect mode. See the "Reset Command" section, next.
See also "Requirements for Reading Array Data" in the
"Device Bus Operations" section for more information. The
Read Operations table provides the read parameters, and
Read Operation Timings diagram shows the timing diagram.
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don't care for this
command. The reset command may be written between the
sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data.
Once erasure begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the device to reading array
data (also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If I/O5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to
access the manufacturer and devices codes, and determine
whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code and another read cycle at XX03h retrieves the
continuation code. A read cycle at address XX01h returns the
device code. A read cycle containing a sector address (SA)
and the address 02h in returns 01h if that sector is protected,
or 00h if it is unprotected. Refer to the Sector Address tables
for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn
initiate the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically provides internally generated program pulses
and verify the programmed cell margin. Table 5 shows the
address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are
longer latched. The system can determine the status of the
program operation by using I/O7, I/O6, or RY/BY (N/A on 32-
pin PLCC & (s)TSOP packages). See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the programming operation. The Byte
Program command sequence should be reinitiated once the
device has reset to reading array data, to ensure data
integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from a “0” back to a
“1”. Attempting to do so may halt the operation and set I/O5 to
“1”, or cause the Data Polling algorithm to indicate the
operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
PRELIMINARY (March, 2005, Version 0.0)
10
AMIC Technology, Corp.

11 Page







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