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PDF D70325L-8 Data sheet ( Hoja de datos )

Número de pieza D70325L-8
Descripción UPD70325L-8
Fabricantes NEC 
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No Preview Available ! D70325L-8 Hoja de datos, Descripción, Manual

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD70325
V25+TM
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA
controller, interrupt controller, etc. are all integrated. The µPD70325 is software compatible with the 16/8-bit single-
chip microcontroller µPD70320 (V25TM). The V25+ greatly improves the DMA responsivity and transfer rate compared
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to the V25.
FEATURES
Software compatible with V25
Software compatible with µPD70108/70116 (in native mode) (some instructions added)
Internal 16-bit architecture and external 8-bit data bus
3-stage pipeline method
Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz)
: 200 ns/10 MHz (external 20 MHz)
Memory space 1 Mbyte
On-chip RAM : 256 words × 8 bits
Register bank (memory mapped method) : 8 banks
Input port (port T) with comparator : 8 bits
I/O lines (input port : 4 bits, input/output ports : 20 bits)
Serial interface : 2 channels
• Internal dedicated baud rate generator
• Asynchronous mode and I/O interface mode
Interrupt controller
• Programmable priority (8 levels)
• 3 types of interrupt response method
Vectored interrupt function, register bank switching function, macro service function
DRAM and pseudo SRAM refreshing function
DMA controller : 2 channels
• 4 types of DMA transfer mode
• Transfer rate Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release
mode)
Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release
mode, or burst mode)
• Address pointer (linear) : 20 bits
• Terminal counter : 16 bits
16-bit timer : 2 channels
Time base counter (20 bits) : 1 channel
On-chip clock generator
Programmable wait function
Standby function (STOP, HALT)
The information in this document is subject to change without notice.
Document No. U12850EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan
The mark shows major revised points.
© 11999965

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D70325L-8 pdf
84-Pin Plastic QFJ
µPD70325L-8
µPD70325L-10
µPD70325
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D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
12 74
13 73
14 72
15 71
16 70
17 69
18 68
19 67
20 66
21 65
22 64
23 63
24 62
25 61
26 60
27 59
28 58
29 57
30 56
31 55
32 54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
P17/READY
P16/SCK0
P15/TOUT
P14/INT/POLL
P13/INTP2/INTAK
P12/INTP1
P11/INTP0
NMI (P10)
P27/HLDRQ
P26/HLDAK
P25/TC1
P24/DMAAK1
P23/DMARQ1
Remark IC: Internally Connected
Cautions 1. Fix IC pin individually to high level via a pull-up resistor externally.
2 Fix EA pin to low level.
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D70325L-8 arduino
µPD70325
(4) Register bank switch instructions
• BRKCS ······ Used to switch register banks
A register bank is switched to the register bank indicated by the lower 3 bits in the 16-bit register
described in the operand. The program is also branched with this instruction to the address
obtained from the PS stored in advance in the new register bank and the vector PC.
The RETRBI instruction is used to return the program from the new register bank.
(Descriptive format)
Mnemonic
BRKCS
Operand
reg16
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• TSKSW ······ Used to switch register banks
Just like the BRKCS instruction, this instruction is also executed to select a register bank. The
program is branched to the address obtained from the PS stored in advance in the new register
bank and the address obtained from the PC save area.
(Descriptive format)
Mnemonic
TSKSW
Operand
reg16
(5) Data transfer instructions
• MOVSPA ··· Used to transfer SS and SP values
This instruction is executed to transfer both SS and SP values before the register bank is switched
to SS and SP of the current (post-switching) register bank.
(Descriptive format)
Mnemonic
MOVSPA
Operand
None
• MOVSPB ··· Used to transfer SS and SP values
This instruction is executed to transfer the SS and SP values of the current (pre-switching)
register bank to the SS and SP of the new register bank indicated by the lower 3 bits in the 16-
bit register described in the operand.
(Descriptive format)
Mnemonic
MOVSPB
Operand
reg16
Some µPD70108/ 70116 instructions should be much cared as shown below when used for the µPD70325.
• I/O instruction, primitive I/O instruction
If PSW IBRK flag is reset (0), an interrupt is generated without executing this instruction. Be sure to set (1)
the IBRK flag when using the I/O instruction.
• FPO instruction
An interrupt is generated without executing this instruction.
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