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PDF W3DG7266V-D2 Data sheet ( Hoja de datos )
| Número de pieza | W3DG7266V-D2 | |
| Descripción | SDRAM UNBUFFERED | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs
W3DG7266V-D2
PRELIMINARY*
512MB – 64Mx72 SDRAM, REGISTER and SPD, w/PLL
FEATURES
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the positive
edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V ± 0.3V Power Supply
168 Pin DIMM JEDEC
• PCB: 30.49mm (1.20”) MAX
www.DataSheet4U.com
DESCRIPTION
The W3DG7266V is a 64Mx72 synchronous DRAM
module which consists of nine 64Mx8 SDRAM components
in TSOP II package, two 18 bit Drive ICs for input control
signal and one 2Kb EEPROM in an 8 pin TSSOP package
for Serial Presence Detect which are mounted on a 168
pin DIMM multilayer FR4 Substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Lead-Free Products
• Vendor source control options
• Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN FRONT PIN BACK PIN FRONT PIN BACK PIN BACK PIN BACK
1 VSS 29 DQM1 57 DQ18 85 VSS 113 DQM5 141 DQ50
2 DQ0 30 CS0# 58 DQ19 86 DQ32 114 *CS1# 142 DQ51
3 DQ1 31 DNU 59 VCC 87 DQ33 115 RAS# 143 VCC
4 DQ2 32 VSS 60 DQ20 88 DQ34 116 VSS 144 DQ52
5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC
6 VCC 34 A2 62 *VREF 90 VCC 118 A3 146 *VREF
7 DQ4 35 A4 63 *CKE1 91 DQ36 119 A5 147 REGE
8 DQ5 36 A6 64 VSS 92 DQ37 120 A7 148 VSS
9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53
10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122 BA0 150 DQ54
11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55
12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS
13 DQ9 41 VCC 69 DQ24 97 DQ41 125 *CK1 153 DQ56
14 DQ10 42 CK0 70 DQ25 98 DQ42 126 A12 154 DQ57
15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58
16 DQ12 44 DNU 72 DQ27 100 DQ44 128 CKE0 156 DQ59
17 DQ13 45 CS2# 73 VCC 101 DQ45 129 *CS3# 157 VCC
18 VCC 46 DQM2 74 DQ28 102 VCC 130 DQM6 158 DQ60
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
20 DQ15 48 DNU 76 DQ30 104 DQ47 132 *A13 160 DQ62
21 CB0 49 VCC 77 DQ31 105 CB4 133 VCC 161 DQ63
22 CB1 50 NC 78 VSS 106 CB5 134 NC 162 VSS
23 VSS 51 NC 79 *CK2 107 VSS 135 NC 163 *CK3
24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC
25 NC 53 CB3 81 NC 109 NC 137 CB7 165 **SA0
26 VCC 54 VSS 82 **SDA 110 VCC 138 VSS 166 **SA1
27 WE# 55 DQ16 83 **SCL 111 CAS# 139 DQ48 167 *SA2
28 DQM0 56 DQ17 84 VCC 112 DQM4 140 DQ49 168 VCC
PIN NAMES
A0 – A12
BA0-1
DQ0-63
CB0-7
CK0
CKE0
CS0#, CS2#
RAS#
CAS#
WE#
DQM0-7
VCC
VSS
*VREF
REGE
SDA
SCL
SA0-2
DNU
NC
Address Input (Multiplexed)
Select Bank
Data Input/Output
Check Bit (Data-In/Data-Out)
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Power Supply for Reference
Register Enable
Serial Data I/O
Serial Clock
Address in EEPROM
Do Not Use
No Connect
* These pins are not used in this module.
** These pins should be NC in the system which does
not support SPD.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3DG7266V-D2
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
VCC, VCCQ = +3.3V ±0.3V
AC CHARACTERISTICS
7 7.5 10
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTE
Access timefrom CLK (pos.edge)
CL = 3
tAC(3)
5.4
5.4
6
CL = 2
tAC(2)
5.4
6
6
Address hold time
tAH 0.8
0.8
1
Address setup time
tAS 1.5
1.5
2
CLK high-level width
tCH 2.5
2.5
3
CLK low-level width
tCL 2.5
2.5
3
Clock cycle time
CL = 3
tCK(3)
7
7.5
8
CL = 2
tCK(2)
7.5
10
10
CKE hold time
tCKH 0.8
0.8
1
CKE setup time
tCKS 1.5
1.5
2
www.DCaS#t,aRSASh#e, CeAtS4#,UW.Ec#o, DmQM hold time
tCMH 0.8
0.8
1
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS 1.5
1.5
2
Data-in hold time
tDH 0.8
0.8
1
Data-in setup time
tDS 1.5
1.5
2
Data-out high-impedance time
CL = 3
tHZ(3)
5.4
5.4
6
CL = 2
tHZ(2)
5.4
6
6
Data-out low-impedance time
tLZ 1 1 1
Data-out hold time (load)
tOH 2.7 2.7 2.7
Data-out hold time (no load)
tOHN 1.8 1.8 1.8
ACTIVE to PRECHARGE command
tRAS 37 120,000 44 120,000 50 120,000
ACTIVE to ACTIVE command period
tRC 60
66
66
ACTIVE to READ or WRITE delay
tRCD 15
20
20
Refresh period
tREF 64 64 64
AUTOREFRESH period
tRFC 66 66 66
PRECHARGE command period tRP 15 20 20
ACTIVE bank a to ACTIVE bank b command tRRD 14 15 15
Transition time
tT 0.3 1.2 0.3 1.2 0.3 1.2
WRITE recovery time
tWR 1 CLK
+
7ns
1 CLK
+
7.5ns
1 CLK
+
7.5ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
27
23
23
10
10
28
7
24
14 15 15 ns 25
Exit SELF REFRESH to ACTIVE command
tXSR 67
75
80
ns 20
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2005
Rev. 3
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet W3DG7266V-D2.PDF ] | |
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