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PDF W3DG6430V-D2 Data sheet ( Hoja de datos )
| Número de pieza | W3DG6430V-D2 | |
| Descripción | SDRAM UNBUFFERED | |
| Fabricantes | White Electronic Designs | |
| Logotipo |  |
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White Electronic Designs
W3DG6430V-D2
PRELIMINARY*
256MB - 32M x 64 BUFFERED SDRAM MODULE
FEATURES
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the positive
edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V ± 0.3V Power Supply
168 pin DIMM JEDEC
DESCRIPTION
The W3DG6430V is a 32M x 64 synchronous DRAM
module which consists of sixteen 32Mx4 SDRAM
components in TSOP II package, three very high speed
buffers for reduced input capacitance, and one 2K
EEPROM in an 8 pin TSSOP package for Serial Presence
Detect which are mounted on a 168 pin DIMM multilayer
FR4 Substrate.
* This product is not fully qualified or characterized and is subject to change without
notice.
www.DataSheet4U.com
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1 VSS 29 DQM1 57 DQ18 85 VSS 113 DQM5 141 DQ50
2 DQ0 30 CS0# 58 DQ19 86 DQ32 114 NC 142 DQ51
3 DQ1 31 DNU 59 VCC 87 DQ33 115 RAS# 143 VCC
4 DQ2 32 VSS 60 DQ20 88 DQ34 116 VSS 144 DQ52
5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC
6 VCC 34 A2 62 NC 90 VCC 118 A3 146 NC
7 DQ4 35 A4 63 NC 91 DQ36 119 A5 147 NC
8 DQ5 36 A6 64 VSS 92 DQ37 120 A7 148 VSS
9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53
10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122 BA0 150 DQ54
11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55
12 VSS 40 VCC 68 VSS 96 VSS 124 VCC 152 VSS
13 DQ9 41 VCC 69 DQ24 97 DQ41 125 CLK1 153 DQ56
14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 NC 154 DQ57
15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58
16 DQ12 44 DNU 72 DQ27 100 DQ44 128 CKE0 156 DQ59
17 DQ13 45 CS2# 73 VCC 101 DQ45 129 NC 157 VCC
18 VCC 46 DQM2 74 DQ28 102 VCC 130 DQM6 158 DQ60
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
20 DQ15 48 DNU 76 DQ30 104 DQ47 132 NC 160 DQ62
21 NC 49 VCC 77 DQ31 105 NC 133 VCC 161 DQ63
22 NC 50 NC 78 VSS 106 NC 134 NC 162 VSS
23 VSS 51 NC 79 CK2 107 VSS 135 NC 163 CLK3
24 NC 52 NC 80 NC 108 NC 136 NC 164 NC
25 NC 53 NC 81 NC 109 NC 137 NC 165 SA0
26 VCC 54 VSS 82 **SDA 110 VCC 138 VSS 166 SA1
27 WE# 55 DQ16 83 **SCL 111 CAS# 139 DQ48 167 SA2
28 DQM0 56 DQ17 84 VCC 112 DQM4 140 DQ49 168 VCC
PIN NAMES
A0 – A11
Address input (Multiplexed)
BA0-1
Select Bank
DQ0-63
Data Input/Output
CLK0,CLK3 Clock input
CKE0
Clock Enable input
CS0#-CS2# Chip select Input
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE# Write Enable
DQM0-7
DQM
VCC Power Supply (3.3V)
VSS Ground
SDA Serial data I/O
SCL Serial clock
DNU Do not use
NC No Connect
SA0-SA2
Address in EEPROM
** These pins should be NC in the system which does
not support SPD.
February 2002
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
W3DG6430V-D2
PRELIMINARY
AC CHARACTERISTICS
Paramater
Access time from CLK
Address hold time
Address setup time
CLK high level width
CLK low level width
Clock cycle time
CKE hold time
CKE setup time
CS, RAS, CAS, WE, DQM hold time
CS, RAS, CAS, WE, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
Data-out low-impedance time
www.DDaatata-oSut hhoeldetimt4eU(lo.acd)om
Data-out hold time (no load)
Active to Precharge command
Active to Active command period
Active to Read or Write delay
Refresh period
Auot refresh period
Precharge command period
Active bank a to Active bank b command
Transition time
CL = 2
CL = 2
CL = 2
Symbol
tAC
tAH
tAS
tCH
tCL
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
tLZ
tOH
tN
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
tT
Write recovery time
tWR
Exit Self Refresh to Active command
tXSR
Notes:
1. The clock frequency must remain constant ( stable clock is defined as a signal cycling within
timing constraints specified for the clock pin) during access or precharge states (READ,
WRITE, including WR and Precharge commands). CKE may be used to reduce the data rate.
2. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference
to VOH or VOL. The last valid data element will meet tOH before going High-Z.
3. Paramater guaranteed by design
4. AC characteristics assume tT = 1ns
5. Auto precharge mode only) The precharge timing budget ( tRP) begins 7ns after the first clock
delay, after the last Write is executed.
6. Precharge mode only.
7. CLK must be toggled a minimum of two times during this period.
133MHz component timing
Min
0.8
1.5
2.5
2.5
7.5
0.8
1.5
0.8
1.5
0.8
1.5
1
3
1.8
37
60
15
66
15
14
0.3
1 CLK + 7ns
Max
5.4
5.4
120,000
64
1.2
67
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
Notes
1
2
3
4
5
6
7
Address hold time
Address setup time
CS, RAS, CAS, WE, DQM hold time
CS, RAS, CAS, WE, DQM setup time
MODULE AC CHARACTERISTIC
Symbol
AH
AS
CMH
CMS
Min
0
4.5
0
4.5
Max
Units
ns
ns
ns
ns
Notes
February 2002
Rev. 0
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet W3DG6430V-D2.PDF ] | |
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