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PDF 79RC32435 Data sheet ( Hoja de datos )

Número de pieza 79RC32435
Descripción IDTTM InterpriseTM Integrated Communications Processor
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! 79RC32435 Hoja de datos, Descripción, Manual

IDTTM InterpriseTM Integrated
Communications Processor
www.DataSheet4U.com
79RC32435
Device Overview
The 79RC32435 is a member of the IDT™ Interprise™ family of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
memory with minimal CPU intervention, using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32435 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
Features
x 32-bit CPU Core
– MIPS32 instruction set
– Cache Sizes: 8KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
– 16 dual-entry JTLB with variable page sizes
– 3-entry instruction TLB
– 3-entry data TLB
– Max issue rate of one 32x16 multiply per clock
– Max issue rate of one 32x32 multiply every other clock
– CPU control with start, stop, and single stepping
– Software breakpoints support
– Hardware breakpoints on virtual addresses
– ICE Interface that is compatible with v2.5 of the EJTAG Spec-
ification
x PCI Interface
– 32-bit PCI revision 2.2 compliant
– Supports host or satellite operation in both master and target
modes
– Support for synchronous and asynchronous operation
– PCI clock supports frequencies from 16 MHz to 66 MHz
– PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
– I2O “like” PCI Messaging Unit
x Ethernet Interface
– 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
– Supports MII or RMII PHY interface
– Supports 64 entry hash table based multicast address filtering
– 512 byte transmit and receive FIFOs
– Supports flow control functions outlined in IEEE Std. 802.3x-
1997
x DDR Memory Controller
– Supports up to 256MB of DDR SDRAM
– 1 chip select supporting 4 internal DDR banks
– Supports a 16-bit wide data port using x8 or x16 bit wide DDR
SDRAM devices
– Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR
SDRAM devices
– Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
– Automatic refresh generation
Block Diagram
ICE
DDR
(16-bit)
MIPS-32
CPU Core
EJTAG
D. Cache
MMU
I. Cache
PMBus
DDR
Controllers
MII/RMII
Interrupt
Controller
:
:
3 Counter
Timers
1 Ethernet
10/100
Interface
IPBusTM
I2C Bus
I2C
Controller
NVRAM
Controller
DMA
Controller
Arbiter
Memory & I/O
Controller
Bus/System
Integrity
Monitor
1 UART
(16550)
GPIO
Interface
SPI
Controller
PCI
Master/Target
Interface
PCI Arbiter
(Host Mode)
Memory &
Peripheral Bus (8-bit)
Serial Channel GPIO Pins SPI Bus
PCI Bus
2005 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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79RC32435 pdf
IDT 79RC32435
Signal
DDRCKP
DDRCSN
DDRDATA[15:0]
DDRDM[1:0]
DDRDQS[1:0]
DDRRASN
DDRVREF
DDRWEN
PCI Bus
PCIAD[31:0]
PCICBEN[3:0]
PCICLK
PCIDEVSELN
PCIFRAMEN
PCIGNTN[3:0]
PCIIRDYN
Type
O
O
I/O
O
I/O
O
I
O
Name/Description
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DDR Positive DDR clock. This signal is the positive clock of the differential
DDR clock pair.
DDR Chip Selects. This active low signal is used to select DDR device(s) on
the DDR bus.
DDR Data Bus. 16-bit DDR data bus is used to transfer data between the
RC32435 and the DDR devices. Data is transferred on both edges of the clock.
DDR Data Write Enables. Byte data write enables are used to enable specific
byte lanes during DDR writes.
DDRDM[0] corresponds to DDRDATA[7:0]
DDRDM[1] corresponds to DDRDATA[15:8]
DDR Data Strobes. DDR byte data strobes are used to clock data between
DDR devices and the RC32435. These strobes are inputs during DDR reads
and outputs during DDR writes.
DDRDQS[0] corresponds to DDRDATA[7:0]
DDRDQS[1] corresponds to DDRDATA[15:8]
DDR Row Address Strobe. The DDR row address strobe is asserted during
DDR transactions.
DDR Voltage Reference. SSTL_2 DDR voltage reference is generated by an
external source.
DDR Write Enable. DDR write enable is asserted during DDR write transac-
tions.
I/O PCI Multiplexed Address/Data Bus. Address is driven by a bus master during
initial PCIFRAMEN assertion. Data is then driven by the bus master during
writes or by the bus target during reads.
I/O PCI Multiplexed Command/Byte Enable Bus. PCI commands are driven by
the bus master during the initial PCIFRAMEN assertion. Byte enable signals are
driven by the bus master during subsequent data phase(s).
I PCI Clock. Clock used for all PCI bus transactions.
I/O PCI Device Select. This signal is driven by a bus target to indicate that the tar-
get has decoded the address as one of its own address spaces.
I/O PCI Frame. Driven by a bus master. Assertion indicates the beginning of a bus
transaction. Negation indicates the last data.
I/O PCI Bus Grant.
In PCI host mode with internal arbiter:
The assertion of these signals indicates to the agent that the internal RC32435
arbiter has granted the agent access to the PCI bus.
In PCI host mode with external arbiter:
PCIGNTN[0]: asserted by an external arbiter to indicate to the RC32435 that
access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
In PCI satellite mode:
PCIGNTN[0]: This signal is asserted by an external arbiter to indicate to the
RC32435 that access to the PCI bus has been granted.
PCIGNTN[3:1]: unused and driven high.
I/O PCI Initiator Ready. Driven by the bus master to indicate that the current datum
can complete.
Table 1 Pin Description (Part 2 of 6)
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79RC32435 arduino
IDT 79RC32435
Function
Serial Peripheral
Interface
I2C-Bus Interface
Ethernet Interfaces
EJTAG / JTAG
System
Pin Name
SCK
SDI
SDO
SCL
SDA
MIICL
MIICRS
MIIRXCLK
MIIRXD[3:0]
MIIRXDV
MIIRXER
MIITXCLK
MIITXD[3:0]
MIITXENP
MIITXER
MIIMDC
MIIMDIO
JTAG_TMS
EJTAG_TMS
JTAG_TRST_N
JTAG_TCK
JTAG_TDO
JTAG_TDI
CLK
EXTBCV
EXTCLK
COLDRSTN
RSTN
Type
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
O
O
O
O
I/O
I
I
I
I
O
I
I
I
O
I
I/O
Buffer
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O Type
High Drive
High Drive
High Drive
Low Drive/STI
Low Drive/STI
STI
STI
STI
STI
STI
STI
STI
Low Drive
Low Drive
Low Drive
Low Drive
Low Drive
STI
STI
STI
STI
Low Drive
STI
STI
STI
High Drive
STI
Low Drive / STI
Internal
Resistor
pull-up
pull-up
pull-up
pull-down
pull-down
pull-up
pull-up
pull-down
pull-down
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-down
pull-up
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Notes1
pull-up on board
pull-up on board
pull-up on board
pull-up on board2
pull-up on board2
pull-up on board
Table 2 Pin Characteristics (Part 2 of 2)
1. External pull-up required in most system applications. Some applications may require additional pull-ups not identified in this table.
2. Use a 2.2K pull-up resistor for I2C pins.
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