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PDF IDT74LVCH16646A Data sheet ( Hoja de datos )
| Número de pieza | IDT74LVCH16646A | |
| Descripción | 3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74LVCH16646A
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
3.3V CMOS 16-BIT BUS
IDT74LVCH16646A
TRANSCEIVER/REGISTER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
www.Data•ShAelelt4inUp.cuotsm, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
The LVCH16646A 16-bit bus transceiver and register is built using
advanced dual metal CMOS technology. This high-speed, low power
device is organized as two independent 8-bit D-type transceivers with 3-
state D-type registers.The controls circuitry is organized for multiplexed
transmission of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register features direction
control (DIR), over-riding Output Enable control (OE) and Select lines (SAB
and SBA) to select either real- time data or stored data. Separate clock inputs
are provided for A and B port registers. Data on the A or B data bus, or both,
can be stored in the internal registers by the low-to-high transitions at the
appropriate clock pins. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16646A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16646A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
56
1OE
1DIR 1
1CLKBA 55
1SBA
1CLKAB
1SAB
54
2
3
5
1A1
One of Eight Channels
1D
C1
1D
C1
29
2OE
2DIR
28
2CLKBA 30
2SBA
2CLKAB
2SAB
31
27
26
52 1B1 2A1 15
One of Eight Channels
1D
C1
1D
C1
42 2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 1999 Integrated Device Technology, Inc.
1
MARCH 1999
DSC-3787/1
1 page  
IDT74LVCH16646A
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
BUS-HOLD CHARACTERISTICS
Symbol Parameter(1)
IBHH Bus-Hold Input Sustain Current VCC = 3V
IBHL
IBHH Bus-Hold Input Sustain Current VCC = 2.3V
IBHL
IBHHO
Bus-Hold Input Overdrive Current VCC = 3.6V
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
www.DataSheet4U.com
Test Conditions
VI = 2V
VI = 0.8V
VI = 1.7V
VI = 0.7V
VI = 0 to 3.6V
INDUSTRIALTEMPERATURERANGE
Min. Typ.(2) Max. Unit
– 75 —
— µA
75 —
—
——
— µA
——
—
— — ±500 µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
VOH Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
IOH = – 6mA
VCC = 2.3V
IOH = – 12mA
VCC = 2.7V
VCC = 3V
VCC = 3V
IOH = – 24mA
VOL OutputLOWVoltage
VCC = 2.3V to 3.6V
IOL = 0.1mA
VCC = 2.3V
IOL = 6mA
IOL = 12mA
VCC = 2.7V
IOL = 12mA
VCC = 3V
IOL = 24mA
Min. Max. Unit
VCC – 0.2
—
V
2—
1.7 —
2.2 —
2.4 —
2—
— 0.2 V
— 0.4
— 0.7
— 0.4
— 0.55
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
CPD
CPD
Parameter
Power Dissipation Capacitance per Transceiver Outputs enabled
Power Dissipation Capacitance per Transceiver Outputs disabled
Test Conditions
CL = 0pF, f = 10Mhz
Typical
60
12
Unit
pF
5
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| PDF Descargar | [ Datasheet IDT74LVCH16646A.PDF ] | |
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