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PDF IDT74LVCH16501A Data sheet ( Hoja de datos )
| Número de pieza | IDT74LVCH16501A | |
| Descripción | 3.3V CMOS 18-BIT REGISTERED BUS TRANSCEIVER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
INDUSTRIALTEMPERATURERANGE
3.3V CMOS 18-BIT
IDT74LVCH16501A
REGISTERED BUS TRANSCEIVER
WITH 5V TOLERANT I/O
AND BUS-HOLD
FEATURES:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
www.Data•ShAelelt4inUp.cuotsm, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
This 18-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power 18-bit registered bus
transceiver combines D-type latches and D-type flip-flops to allow data flow
in transparent latched and clocked modes. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable (LEAB and
LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB
is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition
of CLKAB. OEAB performs the output enable function on the B port. Data
flow from B port to A port is similar but requires using OEBA, LEBA and
CLKBA. Flow-through organization of signal pins simplifies layout. All inputs
are designed with hysteresis for improved noise margin.
The LVCH16501A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16501A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB 1
CLKBA 30
LEBA 28
OEBA 27
CLKAB 55
LEAB 2
3
A1
C
D
C
D
54
B1
CC
DD
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
© 2004 Integrated Device Technology, Inc.
1
JANUARY 2004
DSC-3688/2
1 page  
IDT74LVCH16501A
3.3V CMOS 18-BIT REGISTERED TRANSCEIVER WITH 5 VOLT I/O
SWITCHING CHARACTERISTICS(1)
Symbol Parameter
tPLH PropagationDelay
tPHL Ax to Bx or Bx to Ax
tPLH PropagationDelay
tPHL LEBA to Ax, LEAB to Bx
tPLH PropagationDelay
tPHL CLKBA to Ax, CLKAB to Bx
tPZH OutputEnableTime
tPZL OEBA to Ax, OEAB to Bx
www.DataShetPeHtZ4U.com Output Disable Time
tPLZ OEBA to Ax, OEAB to Bx
tSU Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tH Hold Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tSU Set-up Time, HIGH or LOW
CLK LOW
Ax to LEAB, Bx to LEBA
CLK HIGH
tH Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
tW Pulse Width HIGH, LEAB or LEBA
tW Pulse Width HIGH or LOW, CLKAB or CLKBA
tSK(o) Output Skew(2)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
INDUSTRIALTEMPERATURERANGE
VCC = 2.7V
Min. Max.
1.5 5.2
VCC = 3.3V ± 0.3V
Min. Max.
1.5 4.6
Unit
ns
1.5 6 1.5 5.3 ns
1.5 6 1.5 5.3 ns
1.5 6 1.5 5.6 ns
1.5 6.5 1.5 5.8 ns
3 — 3 — ns
0 — 0 — ns
3 — 3 — ns
2 — 2—
1.5 — 1.5 — ns
3 — 3 — ns
3 — 3 — ns
— — — 500 ps
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IDT74LVCH16501A.PDF ] | |
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