PDF IDT74LVC16373A Data sheet ( Hoja de datos )

Número de pieza	IDT74LVC16373A
Descripción	3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
Fabricantes	Integrated Device Technology
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No Preview Available ! IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDEDCOMMERCIALTEMPERATURERANGE 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O IDT74LVC16373A FEATURES: – Typical tSK(0) (Output Skew) < 250ps – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages www.DataSh–eet4EUx.tceonmded commercial range of -40°C to +85°C – VCC = 3.3V ±0.3V, Normal Range – VCC = 2.7V to 3.6V, Extended Range – CMOS power levels (0.4µ W typ. static) – All inputs, outputs and I/O are 5 Volt tolerant – Supports hot insertion Drive Features for LVC16373A: – High Output Drivers: ±24mA – Reduced system switching noise APPLICATIONS: • 5V and 3.3V mixed voltage systems • Data communication and telecommunication systems DESCRIPTION: The LVC16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVC16373A can be used for implement- ing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8- bit latches or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVC16373A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system. The LVC16373A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. Functional Block Diagram 1OE 1 1LE 48 1D1 47 D CQ 2OE 24 2 1Q1 2LE 25 2D1 36 D CQ 13 2Q1 TO SEVEN OTHER CHANNELS TO SEVEN OTHER CHANNELS EXTENDED COMMERCIAL TEMPERATURE RANGE c 1999 Integrated Device Technology, Inc. 1 MARCH 1999 DSC-4624/1 1 page IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH EXTENDEDCOMMERCIALTEMPERATURERANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 VCC / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF LVC Link TEST CIRCUITS FOR ALL OUTPUTS www.DataSheet4U.com VCC VLOAD Open Pulse (1, 2) Generator VIN VOUT D.U.T. 500Ω GND RT 500Ω CL LVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. SAME PHASE INPUT TRANSITION OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPLH tPHL tPHL VIH VT 0V VOH VT VOL VIH VT 0V LVC Link ENABLE AND DISABLE TIMES CONTROL INPUT ENABLE tPZL DISABLE tPLZ OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V LVC Link NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SET-UP, HOLD, AND RELEASE TIMES SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests OUTPUT SKEW - tsk (x) Switch VLOAD GND Open INPUT tPLH1 tPHL1 OUTPUT 1 tSK (x) tSK (x) OUTPUT 2 LVC Link VIH VT 0V VOH VT VOL VOH VT VOL tPLH2 tPHL2 tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 NOTES: LVC Link 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL PULSE WIDTH LOW-HIGH-LOW PULSE H IG H -LO W -H IG H PULSE tSU tH tREM tSU tH tW VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V LVC Link VT VT LVC Link 5 5 Page

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