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PDF EP1K100 Data sheet ( Hoja de datos )

Número de pieza EP1K100
Descripción Programmable Logic Device Family
Fabricantes Altera 
Logotipo Altera Logotipo



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No Preview Available ! EP1K100 Hoja de datos, Descripción, Manual

September 2001, ver. 3.3
ACEX 1K
Programmable Logic Device Family
®
Data Sheet
Features...
www.DataSheet4U.com
s Programmable logic devices (PLDs), providing low cost
system-on-a-programmable-chip (SOPC) integration in a single
device
– Enhanced embedded array for implementing megafunctions
such as efficient memory and specialized logic functions
– Dual-port capability with up to 16-bit width per embedded array
block (EAB)
– Logic array for general logic functions
s High density
– 10,000 to 100,000 typical gates (see Table 1)
– Up to 49,152 RAM bits (4,096 bits per EAB, all of which can be
used without reducing logic capacity)
s Cost-efficient programmable architecture for high-volume
applications
– Cost-optimized process
– Low cost solution for high-performance communications
applications
s System-level features
– MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or
5.0-V devices
– Low power consumption
– Bidirectional I/O performance (setup time [tSU] and clock-to-
output delay [tCO]) up to 250 MHz
– Fully compliant with the peripheral component interconnect
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
Table 1. ACEXTM 1K Device Features
Feature
Typical gates
Maximum system gates
Logic elements (LEs)
EABs
Total RAM bits
Maximum user I/O pins
EP1K10
10,000
56,000
576
3
12,288
136
EP1K30
30,000
119,000
1,728
6
24,576
171
EP1K50
50,000
199,000
2,880
10
40,960
249
EP1K100
100,000
257,000
4,992
12
49,152
333
13
Altera Corporation
A-DS-ACEX-3.3
1

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EP1K100 pdf
ACEX 1K Programmable Logic Device Family Data Sheet
Table 5 shows ACEX 1K device performance for more complex designs.
These designs are available as Altera MegaCoreTM functions.
Table 5. ACEX 1K Device Performance for Complex Designs
Application
LEs
Used
16-bit, 8-tap parallel finite impulse response (FIR)
filter
8-bit, 512-point Fast Fourier transform (FFT)
function
a16450 universal asynchronous
receiver/transmitter (UART)
597
1,854
342
-1
192
23.4
113
36
Performance
Speed Grade
-2 -3
156 116
28.7 38.9
92 68
28 20.5
Units
MSPS
µs
MHz
MHz
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Each ACEX 1K device contains an embedded array and a logic array. The
embedded array is used to implement a variety of memory functions or
complex logic functions, such as digital signal processing (DSP), wide
data-path manipulation, microcontroller applications, and data-
transformation functions. The logic array performs the same function as
the sea-of-gates in the gate array and is used to implement general logic
such as counters, adders, state machines, and multiplexers. The
combination of embedded and logic arrays provides the high
performance and high density of embedded gate arrays, enabling
designers to implement an entire system on a single device.
ACEX 1K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers EPC16, EPC2, EPC1, and EPC1441 configuration devices,
which configure ACEX 1K devices via a serial data stream. Configuration
data can also be downloaded from system RAM or via the Altera
MasterBlasterTM, ByteBlasterMVTM, or BitBlasterTM download cables.
After an ACEX 1K device has been configured, it can be reconfigured in-
circuit by resetting the device and loading new data. Because
reconfiguration requires less than 40 ms, real-time changes can be made
during system operation.
ACEX 1K devices contain an interface that permits microprocessors to
configure ACEX 1K devices serially or in parallel, and synchronously or
asynchronously. The interface also enables microprocessors to treat an
ACEX 1K device as memory and configure it by writing to a virtual
memory location, simplifying device reconfiguration.
13
Altera Corporation
5

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EP1K100 arduino
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 3. ACEX 1K EAB in Dual-Port RAM Mode
Clock A
Port A
address_a[]
data_a[]
we_a
clkena_a
Port B
address_b[]
data_b[]
we_b
clkena_b
Clock B
Figure 4. ACEX 1K Device in Single-Port RAM Mode
Dedicated
Clocks
Dedicated Inputs
& Global Signals
Chip-Wide
Reset
Row Interconnect
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2
4
8, 4, 2, 1
DQ
RAM/ROM
256 × 16
Data
In
512
1,024
×
×
8
4
2,048 × 2
Data Out
4, 8, 16, 32
DQ
4, 8
EAB Local
Interconnect (1)
8, 9, 10, 11
DQ
Address
4, 8, 16, 32
DQ
Write Enable
13
Column Interconnect
Note:
(1) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB
local interconnect channels.
Altera Corporation
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