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Número de pieza ICS9LPR426A
Descripción Low Power Programmable Timing Control Hub
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



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No Preview Available ! ICS9LPR426A Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS9LPR426A
Advance Information
Low Power Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
Low Power CK410M Compliant Main Clock
Output Features:
• 2 - 0.7V push-pull differential CPU pairs
• 5 - 0.7V push-pull differential PCIEX pairs
• 1 - 0.7V push-pull differential SATA pair
www.DataSheet4U.c1om- 0.7V push-pull differential CPU/PCIEX selectable pair
• 1 - 0.7V push-pull differential 27MHz/LCDCLK/PCIEX
selectable pair
• 4 - PCI (33MHz)
• 2 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 2 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• PCIEX outputs cycle-cycle jitter < 125ps
• SATA outputs cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 500ps
• +/- 100ppm frequency accuracy on CPU, PCIEX and
SATA clocks
• +/- 100ppm frequency accuracy on USB clocks
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCIEX
• Supports programmable spread percentage and
frequency
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• PEREQ# pins to support PCIEX power management.
• Low power differential clock outputs (No 50W resistor
to GND needed)
Pin Configuration
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
*SELPCIEX0_LCD#PCICLK5 5
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
*SELLCD_27#/PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
FSLA/USB_48MHz 12
GND 13
DOTT_96MHzL 14
DOTC_96MHzL 15
FSLB/TEST_MODE 16
27FIX/LCD_SSCGT/PCIeT_L0 17
27SS/LCD_SSCGC/PCIeC_L0 18
PCIeT_L1 19
PCIeC_L1 20
VDDPCIEX 21
PCIeT_L2 22
PCIeC_L2 23
PCIeT_L3 24
PCIeC_L3 25
SATACLKT_L 26
SATACLKC_L 27
VDDPCIEX 28
56 PCICLK2/REQ_SEL**
55 PCI&PCIEX_STOP#
54 CPU_STOP#
53 REF1/FSLC/TEST_SEL
52 REF0
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
45 GND
44 CPUT_L0
43 CPUC_L0
42 VDDCPU
41 CPUT_L1
40 CPUC_L1
39 VDD
38 GNDA
37 VDDA
36 CPUITPT_L2/PCIeT_L6
35 CPUITPC_L2/PCIeC_L6
34 VDDPCIEX
33 PEREQ1#/PCIeT_L5
32 PEREQ2#/PCIeC_L5
31 PCIeT_L4
30 PCIeC_L4
29 GND
56-TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
1346–10/23/07
Functionality Table
Bit 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 2 Bit 1 Bit 0
Bit 3
FSLC FSLB FSLA
CPU
MHz
PCIEX
MHz
0 0 0 0 266.66 99.75
0 0 0 1 133.33 99.75
0 0 1 0 200.00 99.75
0 0 1 1 166.66 99.75
0 1 0 0 333.33 99.75
0 1 0 1 100.00 99.75
0 1 1 0 400.00 99.75
0 1 1 1 200.00 99.75
1 0 0 0 266.66 99.75
1 0 0 1 133.33 99.75
1 0 1 0 200.00 99.75
1 0 1 1 166.66 99.75
1 1 0 0 333.33 99.75
1 1 0 1 100.00 99.75
1 1 1 0 400.00 99.75
1 1 1 1 200.00 99.75
0 0 0 0 269.33 100.75
0 0 0 1 271.99 101.75
0 0 1 0 274.66 102.74
0 0 1 1 277.33 103.74
0 1 0 0 279.99 104.74
0 1 0 1 282.66 105.74
0 1 1 0 285.33 106.73
0 1 1 1 287.99 107.73
1 0 0 0 269.33 108.73
1 0 0 1 271.99 109.73
1 0 1 0 274.66 110.72
1 0 1 1 277.33 111.72
1 1 0 0 279.99 112.72
1 1 0 1 282.66 113.72
1 1 1 0 285.33 114.71
1 1 1 1 287.99 115.71
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
SATA
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

1 page




ICS9LPR426A pdf
Integrated
Circuit
Systems, Inc.
Table 1: CPU PLL Spread Frequency Selection Table
FS4
(B0b4)
0
FS3 (B0b3)
0
FSLC
(B0b2)
0
00
0
00
0
00
0
00
1
00
1
00
1
0
www.DataSheet4U.com
0
0
1
1
0
01
0
01
0
01
0
01
1
01
1
01
1
01
1
10
0
10
0
10
0
10
0
10
1
10
1
10
1
10
1
11
0
11
0
11
0
11
0
11
1
11
1
11
11
1
1
ICS9LPR426A
Advance Information
FSLB
(B0b1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FSLA
(B0b0)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
266.66
133.33
200.00
166.66
333.33
100.00
400.00
200.00
269.33
271.99
274.66
277.33
279.99
282.66
285.33
287.99
269.33
271.99
274.66
277.33
279.99
282.66
285.33
287.99
Spread %
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
+/- 0.25 Center
1346—10/23/07
5

5 Page





ICS9LPR426A arduino
Integrated
Circuit
Systems, Inc.
ICS9LPR426A
Advance Information
I2C Table: Output Control Register
Byte 5
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PCIEXT/C4
Reserved
Reserved
SATACLK
PCIEXT/C3
PCIEXT/C2
PCIEXT/C1
Bit 0
PCIEXT/C0
Control Function
Allow assertion of PCI_STOP# or
setting of PCI_STOP control bit in I2C
register to stop PCIEX clocks.
RW
RW
RW
RW
RW
RW
RW
RW
0
Free-Running
-
-
Free-Running
Free-Running
Free-Running
Free-Running
Free-Running
1
Stoppable
-
-
Stoppable
Stoppable
Stoppable
Stoppable
Stoppable
PWD
0
X
X
0
0
0
0
0
I2C Table: Amplitude Control Register
www.DataSheet4BUyt.eco6m
Name
Control Function
Bit 7
Bit 6
Diff AMP
Diff AMP
CPU Differential output Amplitude
Control
Bit 5
Reserved
Reserved
Bit 4
Reserved
Reserved
Bit 3
Bit 2
Diff AMP
Diff AMP
DOT96 Differential output Amplitude
Control
Bit 1
Diff AMP
SATACLK Differential output Amplitude
Bit 0
Diff AMP
Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
00 = 700mV
10 = 800mV
-
-
00 = 700mV
10 = 800mV
00 = 700mV
10 = 800mV
1
01 = 900mV
11 = 1000mV
-
-
01 = 900mV
11 = 1000mV
01 = 900mV
11 = 1000mV
PWD
0
0
X
X
0
0
0
0
I2C Table: Revision and Vendor ID Register
Byte 7
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
RID3
RID2
RID1
RID0
VID3
VID2
VID1
Bit 0
VID0
Control Function
Revision ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
001 = ICS
-
1 PWD
-0
-0
-0
-0
-0
-0
-0
-1
I2C Table: Byte Count Register
Byte 8
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BC7
BC6
BC5
BC4
BC3
BC2
BC1
Bit 0
BC0
Control Function
Byte Count Programming b(7:0)
Type
R
R
R
RW
RW
RW
RW
RW
01
Writing to this register will configure how many bytes will be
read back, default is 0F = 15 bytes.
PWD
0
0
0
0
1
1
1
1
I2C Table: Watch Dog Timer Control Register
Byte 9
Name
Control Function
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
HWD_EN
SWD_EN
WD Hard Status
WD Soft Status
WDTCtrl
HWD2
HWD1
Watchdog Hard Alarm Enable
Watchdog Soft Alarm Enable
WD Hard Alarm Status
WD Soft Alarm Status
Watch Dog Alarm Time base Control
WD Hard Alarm Timer Bit 2
WD Hard Alarm Timer Bit 1
Bit 0
HWD0
WD Hard Alarm Timer Bit 0
Type
RW
RW
R
R
RW
RW
RW
RW
01
Disable
Enable
Disable
Enable
Normal
Alarm
Normal
Alarm
290ms Base
1160ms Base
These bits represent X*290ms (or 1.16S) the watchdog timer
waits before it goes to alarm mode. Default is 7 X 290ms =
2s.
PWD
0
0
X
X
0
1
1
1
1346—10/23/07
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