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Número de pieza | S29JL064H | |
Descripción | 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only | |
Fabricantes | SPANSION | |
Logotipo | ||
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No Preview Available ! S29JL064H
64 Megabit (8 M x 8-Bit/4 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Read/Write
Flash Memory
Distinctive Characteristics
PRELIMINARY
Architectural Advantages
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
www.DataSheet4U—.comZero latency between read and write operations
Flexible Bank architecture
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
Manufactured on 0.13 µm process technology
SecSi™ (Secured Silicon) Sector: Extra 256 Byte
sector
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function.
— Customer lockable: One-time programmable only.
Once locked, data cannot be changed
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
Compatible with JEDEC standards
— Pinout and software compatible with single-power-
supply flash standard
Package options
63-ball Fine Pitch BGA
48-pin TSOP
Performance Characteristics
High performance
— Access time as fast as 55 ns
— Program time: 4 µs/word typical using accelerated
programming function
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
Cycling Endurance: 1 million cycles per sector
typical
Data Retention: 20 years typical
Software Features
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
— Suspends erase operations to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation.
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
Hardware Features
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
Sector protection
— Hardware method to prevent any program or erase
operation within a sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
Publication Number S29JL064H Revision A Amendment 1 Issue Date March 26, 2004
This document contains information on a product under development at FASL LLC. The information is intended to help you evaluate this product. FASL LLC reserves the
right to change or discontinue work on this proposed product without notice.
1 page Preliminary
Product Selector Guide
Part Number
Speed Option
Standard Voltage Range: VCC = 2.7–3.6 V
Max Access Time (ns), tACC
CE# Access (ns), tCE
OE# Access (ns), tOE
Block Diagram
www.DataSheet4VUCC.com
VSS
S29JL064H
55 60 70
55 60 70
55 60 70
25 25 30
OE# BYTE#
A21–A0
Mux
Bank 1 Address
Bank 1
X-Decoder
90
90
90
35
RY/BY#
A21–A0
RESET#
WE#
CE#
BYTE#
WP#/ACC
DQ0–DQ15
STATE
CONTROL
&
COMMAND
REGISTER
Bank 2 Address
Bank 2
X-Decoder
Status
Control
Bank 3 Address
X-Decoder
Bank 3
DQ15–DQ0
Mux
A21–A0
Mux
Bank 4 Address
X-Decoder
Bank 4
March 26, 2004 S29JL064HA1
S29JL064H
5
5 Page Preliminary
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or
word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only
data I/O pins DQ7–DQ0 are active and controlled by CE# and OE#. The data I/
O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the
LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE#
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pins to VIL. CE# is the power control and selects the device. OE# is the output
control and gates array data to the output pins. WE# should remain at VIH. The
BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. Each bank remains enabled for read access until the command register
contents are altered.
Refer to the AC Read-Only Operations table for timing specifications and to 14 for
the timing diagram. ICC1 in the DC Characteristics table represents the active cur-
rent specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data
to the device and erasing sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facilitate faster programming.
Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word or byte, instead of four. The “Byte/Word Program Command
Sequence” section has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device.
Table 3 indicates the address space that each sector occupies. Similarly, a “sector
address” is the address bits required to uniquely select a sector. The “Command
Definitions” section has details on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.
The device address space is divided into four banks. A “bank address” is the ad-
dress bits required to uniquely select a bank.
ICC2 in the DC Characteristics table represents the active current specification for
the write mode. The AC Characteristics section contains timing specification ta-
bles and timing diagrams for write operations.
March 26, 2004 S29JL064HA1
S29JL064H
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet S29JL064H.PDF ] |
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