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PDF T6B65AFG Data sheet ( Hoja de datos )
| Número de pieza | T6B65AFG | |
| Descripción | COLUMN DRIVER LSI | |
| Fabricantes | Toshiba Semiconductor | |
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T6B65AFG
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6B65AFG
Column Driver LSI for Dot Matrix Graphic LCD’s
Manufactured using the CMOS process, the T6B65AFG is a
column (segment) driver for small-to-medium-sized dot matrix
graphic LCDs. Use of the T6B65AFG enables power dissipation to
be reduced. It is designed to connect directly to an 8-bit
microprocessor unit. The MPU can program all operating modes
for the T6B65AFG asynchronously.
www.DataSheet4U.com The T6B65AFG stores display data transferred from an MPU
in its internal display RAM. The contents of the internal display
RAM correspond to the image on the LCD screen and are used to
generate the LCD drive signal.
Three T6B65AFGs can be combined with a Toshiba T6B66BFG
row (common) driver to drive a 240-dot by 65-dot LCD screen.
The T6B65AFG is lead (Pb)-free product.
Features
QFP100-P-1420-0.65Q
Weight: 1.6 g (typ.)
Dot matrix graphic LCD column driver with display RAM
Display RAM capacity
: 64 lines × 10 pages × 8 bits = 5120 bits (display area)
1 line × 10 pages × 8 bits = 80 bits (flag area)
Total = 5200 bits
LCD drive outputs
: 80
Interface
: 80-family MPU (8-bit)
RAM data directly echoed to LCD
(1) RAM bit data = 1 …………… ON
(2) RAM bit data = 0 …………… OFF
Duty: Can be controlled by the T6B66BFG.
Display OFF functions
Various functions
X/Y-counter selection, Up/Down mode selection, X-address setting,
Y-address setting, Display Start Line setting, “Status Read”, display data read/write
Low power consumption
Logic power supply
: 2.7 to 5.5 V
CMOS Si-Gate process
100-pin-plastic flat package
1 2005-06-01
1 page  
T6B65AFG
● Z-address counter
The Z-address counter holds the 6-bit datum that indicates the display start line. This value is preset by the
PM signal. The value indicates the address of the display start line, which is the line that appears at the top
of the screen.
● Counter Up / Down register
This register determines the counter and Up / Down mode. When the X-counter / Up mode is selected,
reading or writing to the RAM causes the X-counter to increment automatically.
When the X-counter / Down mode is selected, reading or writing to the RAM causes the X-counter to
decrement automatically. When the Y-counter / Up mode is selected, reading or writing to the RAM causes
the Y-counter to increment automatically. When the Y-counter / Down mode is selected, reading or writing to
the RAM causes the Y-counter to decrement automatically.
● Display ON / OFF register
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This 1-bit register holds the ON / OFF state. In the OFF state, the output is ignored. In the ON state, the
data in the display RAM is displayed.
The data in the display RAM is independent of the value of the display ON / OFF setting.
● Busy flag
The Busy flag is set when an instruction other than the Status Read instruction is executed. Using Status
Read, you can find out whether the Busy flag has been set or not. While the Busy flag is set, the T6B65A
cannot accept any instruction other than Status Read.
Ensure, therefore, that the Busy flag is reset before an instruction is issued.
The Busy state time (T) is always as follows:
1 / F ≤ T ≤ 2 / F [seconds] F: φ frequency (one half of the T6B66BFG's oscillation frequency)
● Latch
The rising edge of CL latches data from the display RAM.
● Column driver circuit and LCD voltage generation circuit
The column driver circuit consists of 80 driver circuits. The combination of display data from latches and the
M signal selects one of the four LCD levels. Details of the voltage generation circuit and column driver
circuit are shown in the diagram below:
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5 Page 
T6B65AFG
Test Conditions (2)
(Unless otherwise noted, VSS = 0, VDD = 5.0 V ± 10%, VLC5 = VDD − 16 V, Ta = −20 to 75°C)
Item
Operating Supply (1)
Operating Supply (2)
Input
Voltage
H Level
L Level
Output
Voltage
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H Level
L Level
Symbol
VDD
VLC5
Test
Circuit
―
―
Test Condition
―
―
VIH ―
―
VIL ―
―
VOH
― IOH = −400 µA
VOL ― IOL = 400 µA
Min Typ.
4.5
VDD
−16.0
0.7
VDD
0
―
―
―
―
VDD
−0.4
―
――
Max
5.5
VDD
−4.0
VDD
0.3
VDD
―
0.4
Unit Pin Name
V VDD
V VLC5
V CL, PM, /φ
DB0 to DB7,
D / I, / WR,
V / CE, / RST
V
DB0 to DB7
V
Column Output
Resistance
Input Leakage
Operating Frequency
Current Consumption
(1)
Current Consumption
(2)
Current Consumption
(3)
Rcol
IIL
fφ
IDD1
IDD2
IDD3
―
VDD − VLC5 = 11.0 V
Load current = ±100 µA
―
― VIN = VDD to GND
−1
― ― 10
― (Note 1) ―
― (Note 2) ―
― (Note 3) −1
―
7.5
kΩ
SEG1 to
SEG80
DB0 to DB7,
―
1
µA
D / I, / WR,
/ CE, / RST,
CL, PM, /φ
― 250 kHz / φ
220 330 µA VDD
35 50 µA VDD
― 1 µA VDD
Note 1: Current consumption while the internal data receiver is operating:
VDD = 4.0 to 5.5 V, VLC5 = VDD − 16 V, Ta = 25°C
1/9 bias, 1/65 duty, no load, fPM = 35 Hz, fCE = 1 MHz
Note 2: Current consumption while the internal data receiver is inactive:
VDD = 4.0 to 5.5 V, VLC5 = VDD − 16 V, Ta = 25°C
1/9 bias, 1/65 duty, no load
Note 3: Current consumption in Low Power mode ( / STB pin of T6B66BFG = L):
VDD = 5.0 V, VLC5 = 0 V, Ta = 25°C, no load
11 2005-06-01
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet T6B65AFG.PDF ] | |
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