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PDF DS1482 Data sheet ( Hoja de datos )
| Número de pieza | DS1482 | |
| Descripción | 1-Wire Level Shifter and Line Driver | |
| Fabricantes | Dallas Semiconductor | |
| Logotipo |  |
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FEATURES
§ Works with All iButtons® and 1-Wire®
Devices
§ Communicates at Regular and Overdrive 1-
Wire Speed (Host-Dependent)
§ Separate Interface Power Supply to Level
Shift to Non-5V Systems
§ External Strong-Pullup Control Pin can be
Used to Provide Low-On-Resistance-High
www.DataShCeuertr4eUn.tcPoomwer Source
§ Load Sensor to Detect when Strong-Pullup
Power Delivery is no Longer Needed
§ Power Delivery DONE Signal can be
Connected to Host Interrupt
§ Low-Cost 16-Pin SO Surface-Mount Package
§ Operating Temperature Range: -40°C to
+85°C
DS1482
1-Wire Level Shifter and Line Driver
with Load Sensor
PIN ASSIGNMENT
1VCCQ
N.C. 2
SPU 3
START 4
TXD 5
N.C. 6
GND 7
N.C. 8
16 VCC
15 N.C.
14 PCTLZ
13 DONE
12 RXD
11 N.C.
10 I/O
9 N.C.
ORDERING INFORMATION
DS1482S
SO-16
DS1482S/T&R
SO-16, Tape-and-Reel
Contact the factory for versions with different
signal polarities.
DESCRIPTION
The DS1482 is a simple 1-Wire line driver with load sensor and level shifter, designed to function as an
interface between a 3V host system and a 1-Wire system that runs on 5V. Two supplies are provided, a
5V supply for the 1-Wire operations (VCC) and an interface supply (VCCQ). The DS1482 can connect
directly to a synchronous serial port if it supports the appropriate bit rates to generate 1-Wire timing.
Figure 1 shows the DS1482 block diagram. TXD is buffered and controls an N-channel transistor, which
drives the 1-Wire pin I/O low, e.g., to initiate a time slot. The logic level of the I/O pin is returned
through a level-shifting buffer to the RXD pin for the host processor to read. Figure 3 shows the
relationship of these signals in case of a 1-Wire read time slot.
The SPU input generates a control signal (PCTLZ) for an external low-impedance PMOS transistor
(Figure 2) that bypasses the 1-Wire pullup resistor (RPUP) to provide power for 1-Wire devices with a
high-load current. PCTLZ is gated by the inverted TXD signal. This prevents a high through-current in
case TXD and SPU are high at the same time.
The DS1482 contains a high-precision comparator because it is important for the host micro to know
when the high load on the 1-Wire side is no longer active. As shown in Figure 4, the high current load
causes a small drop of the voltage on the I/O pin. The comparator detects when the high current phase
ends, and enables DONE after the deglitching time tCF is over. The START signal allows the host micro
to selectively enable DONE.
iButton and 1-Wire are registered trademarks of Dallas Semiconductor.
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Figure 7. Timing References SPU to PCTLZ
SPU
tSP
PCTLZ
tF
0.7 x VCCQ
0.2 x VCCQ
tSP
0.9 x VCC
0.1 x VCC
tR
Figure 8. Timing References START to DONE
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START
DONE
tR
0.2 x VCCQ
tSD
0.9 x VCCQ
0.1 x VCCQ
tF
DS1482
5 of 7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet DS1482.PDF ] | |
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