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PDF LM2724AMX Data sheet ( Hoja de datos )

Número de pieza LM2724AMX
Descripción High Speed 3A Synchronous MOSFET Driver
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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June 2003
LM2724A
High Speed 3A Synchronous MOSFET Driver
General Description
The LM2724A is a dual N-channel MOSFET driver which
can drive both the top and bottom MOSFETs in a push-pull
structure simultaneously. The LM2724A takes a logic input
and splits it into two complimentary signals with a typical
20ns dead time in between. The built-in cross-conduction
protection circuitry prevents the top and bottom MOSFETs
from turning on simultaneously. With a bias voltage of 5V, the
peak sourcing and sinking current for each driver of the
LM2724A is about 3A. Input UVLO (Under-Voltage-Lock-
Out) ensures that all the driver outputs stay low until the
supply rail exceeds the power-on threshold during system
power on, or after the supply rail drops below power-on
threshold by a specified hysteresis during system power
down. The cross-conduction protection circuitry detects both
driver outputs and will not turn on a driver until the other
driver output is low. The top gate voltage needed by the top
MOSFET is obtained through an external boot-strap struc-
ture. When not switching, the LM2724A only draws up to
195µA from the 5V rail. The synchronization operation of the
bottom MOSFET can be disabled by pulling the SYNC pin to
ground.
Features
n Shoot-through protection
n Input Under-Voltage-Lock-Out
n 3A peak driving current
n 195µA quiescent current
n 28V input voltage in buck configuration
n SO-8 and LLP packages
Applications
n High Current DC/DC Power Supplies
n High Input Voltage Switching Regulators
n Fast Transient Microprocessors
n Notebook Computers
Typical Application
20073501
© 2003 National Semiconductor Corporation DS200735
www.national.com

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LM2724AMX pdf
Electrical Characteristics
LM2724A (Continued)
VCC = BOOT = SYNC = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for
TA = TJ = +25˚C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Condition
Min
Typ
Max
Units
Ileak_IN
IN Pin Leakage Current
IN = 0V, Source Current
IN = 5V, Sink Current
2 µA
10
ton_min1
Minimum Positive Pulse
Width at IN Pin
160
(Note 5)
ton_min2
Minimum Positive Pulse
Width at IN Pin for HG to
Respond
45
(Note 6)
ton_min3
Minimum Positive Pulse
Width at IN Pin for LG to
Respond
10
ns
(Note 7)
toff_min1
Minimum Negative Pulse
Width at IN Pin for LG to
Respond
40
(Note 8)
toff_min2
Minimum Negative Pulse
Width at IN Pin for HG to
Respond
5
(Note 9)
VIH_IN
VIL_IN
IN High Level Input
Voltage
IN Low Level Input
Voltage
When IN pin goes high from
0V
When IN pin goes low from
5V
55%
25%
VCC
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates
correctly. The gaurnteed specifications apply only for the listed test conditions. Some performance characteristics may degrade when the part is not operated under
listed conditions.
Note 2: If BOOT voltage exceeds this value, the ESD structure will degrade.
Note 3: Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, θJA, and the
ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX-TA) / θJA. The junction-to-
ambient thermal resistance, θJA, for LM2724A is 172˚C/W. For a TJMAX of 150˚C and TA of 25˚C, the maximum allowable power dissipation is 0.7W. The θJA, for
LM2724A LLP package is 39˚C/W. For a TJMAX of 150˚C and TA of 25˚C, the maximum allowable power dissipation is 3.2W.
Note 4: ESD machine model susceptibility is 200V.
Note 5: If the positive pulse width at IN pin is below this value but above ton_min2, the pulse is internally stretched to ton_min1, so the HG width will be a constant
value.
Note 6: If the positive pulse width at IN pin is below this value but above ton_min3, then HG stops responding while LG still responds to the pulse.
Note 7: If the positive pulse width at IN pin is below this value, the pulse will be completely ignored. Neither HG or LG will respond to it.
Note 8: If the negative pulse width at IN pin is below this value but above toff_min2, then LG stops responding while HG still responds.
Note 9: If the negative pulse width at IN pin is below this value, the pulse will be completely ignored. Neither HG or LG will respond to it.
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