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PDF S1M8831A Data sheet ( Hoja de datos )

Número de pieza S1M8831A
Descripción (S1M8831A / S1M8833) FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8831A/33
INTRODUCTION
The S1M8831A/33 is a Fractional-N frequency synthesizer with integrated
prescalers, designed for RF operation up to 1.2GHz/K-PCS and for IF
operation up to 520MHz. The fractional-N synthesizer allows fast-locking,
low phase noise phase-locked loops to be built easily, thus having rapid
channel switching and reducing standby time for extended battery life. The
S1M8831A/33 based on - fractional-N techniques solves the fractional
spur problems in other fractional-N synthesizers based on charge pump
compensation. The synthesizer also has an additional feature that the
www.DataSheePt4CUS.c/oCmDMA channel frequency in steps of 10kHz can be accurately
programmed.
24-QFN-3.5×4.5
The S1M8831A/33 contains dual-modulus prescalers. The S1M8831A RF
synthesizer adopts an 8/9 prescaler (16/17 for the S1M8833) and the IF
synthesizer adopts an 8/9 prescaler. Phase detector gain is user-programmable for maximum flexibility to
address IS-95 CDMA and IMT2000. Various program-controlled power down options as well as low supply
voltage help the design of wireless cell phones having minimum power consumption.
Using the Samsung's proprietary digital phase-locked-loop technique, the S1M8831A/33 has a linear phase
detector characteristic and can be used for very stable, low noise PLLs. Supply voltage can range from 2.7V to
4.0V. The S1M8831A/33 is available in a 24-QFN package.
FEATURES
High operating frequency dual synthesizer
— S1M8831A: 0.71 to 1.2GHz(RF)/ 45 to 520MHz(IF)
— S1M8833: 1.6 to 1.65GHz(RF)/ 45 to 520MHz(IF)
Operating voltage range: 2.7 to 4.0V
Low current consumption (S1M8831A: 5.0mA, S1M8833: 7.0mA)
Selectable power saving mode (ICC = 1uA typical @ 3V)
Dual-modulus prescaler and Fractional-N/Integer-N:
— S1M8831A
— S1M8833
— S1M8831A/33
(RF) 8/9
(RF) 16/17
(IF) 8/9
Fractional-N
Fractional-N
Integer-N
Excellent in-band phase noise ( – 85dBc/Hz @ PCS, -90dBc/Hz @CDMA)
Improved fractional spurious performance ( < 80dBc)
Frequency resolution (= 10kHz/64 @ fref = 9.84MHz)
Fast channel switching time: < 500us
Programmable charge pump output current: from 50uA to 800uA in 50uA steps
Programmability via on-chip serial bus interface
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S1M8831A pdf
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8831A/33
PIN DESCRIPTION
Pin No.
1
2
3
4
www.DataSheet4U.c5om
6
Symbol
VDDRF
VPRF
CPoRF
DGND
finRF
finRF
7 GNDRF
8 OSCx
9 OSCin
10 foLD
11 RF_EN
12 IF_EN
13 CLOCK
14 DATA
15 LE
16 GNDIF
17 finIF
18 finIF
19 DGND
20 CPoIF
I/O Description
– RF PLL power supply(2.7V to 4.0V). Must be equal to VDDIF.
– Power supply for RF charge pump. Must be VDDRF and VDDIF.
O RF charge pump output. Connected to an external loop filter.
– Ground for RF PLL digital circuitry.
I RF prescaler input. Small signal input from the external VCO.
I RF prescaler complementary input. For a single-ended output RF VCO, a
bypass capacitor should be placed as close as possible to this pin and be
connected directly to the ground plane.
– Ground for RF PLL analog circuitry.
I RF R counter input (IF_N[22]=0) or not-use (IF_N[22]=1) which can be
configured depending on the state of the program bit IF_N[22].
I Oscillator input to drive both the IF and RF R counter inputs (IF_N[22]=1) or
only the IF R counter (IF_N[22]=0) which can be configured depending on
the state of the program bit IF_N[22].
O Multiplexed output of N or R divider and RF/IF lock detect.
I RF PLL Enable (enable when high, power down when low).
Controls the RF PLL to power down directly, not depending on a program
control. Also sets the charge pump output to be in TRI-STATE when LOW.
Powers up when HIGH depends on the state of RF_CTL_WORD.
I IF PLL Enable(enable when high, power-down when low).
Controls the IF PLL to power down directly. The same as RF_EN except
that power-up depends on the state of IF_CTL_WORD.
I CMOS clock input. Data for the various counters is clocked into the 24-bit
shift register on the rising edge.
I Binary serial data input. Data entered MSB (Most Significant Bit) first.
I Load enable when LE goes HIGH. High impedance CMOS input.
– Ground for IF analog circuitry.
I IF Prescaler complementary input. For a single-ended output IF VCO, a
bypass capacitor should be placed as close as possible to this pin.
I IF prescaler input. Small signal input from the VCO.
– Ground for IF PLL digital circuitry.
O IF charge pump output. Connected to an external loop filter.
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S1M8831A arduino
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8831A/33
ELECTRICAL CHARACTERISTICS (Continued)
(VDD = 3.0V, VP = 3.0V, Ta = 25°C, unless otherwise specified.)
Characteristic
Charge pump leakage current
Sink vs. Source mismatch
www.DataSheetO4Uu.ctopmut current magnitude
variation vs. Voltage
Output current vs.
Temperature
Serial Data Control
CLOCK frequency
CLOCK pulse width high
CLOCK pulse width low
DATA set up time to CLOCK
rising edge
DATA hold time after CLOCK
rising edge
LE pulse width
CLOCK rising edge to LE
rising edge
Symbol
ICPL
ICP-SIINK vs
ICP-SOURCE
ICP vs VCP
ICP vs TA
Test Conditions
0.5V VCP VP-
0.5V
VCP = VP/2
0.5V VCP
VP-0.5V
VCP = VP/2
fCLOCK
tCWH
tCWL
tDS
tDH
tLEW
tCLE
Min.
-2.5
50
50
50
10
50
50
Typ.
3
10
10
Max.
+2.5
10
15
10
Unit
nA
%
%
%
MHz
ns
ns
ns
ns
ns
ns
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