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PDF ICS952906A Data sheet ( Hoja de datos )

Número de pieza ICS952906A
Descripción Programmable Timing Control Hub
Fabricantes ICS 
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Integrated
Circuit
Systems, Inc.
ICS952906A
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
VIA VN800/CN700/P4M800 style chipset for P4 processor
Output Features:
• 3 - 0.7V current-mode differential CPU pairs
• 10 - PCI, 3 free running, 33MHz
• 2 - REF, 14.318MHz
www.DataSheet4U.c3om- 3V66, 66.66MHz
• 1 - 48MHz
• 1 - 24/48MHz
• 2 - 25MHz @ 2.5V
Features/Benefits:
• Programmable output frequency.
• Programmable asynchronous 3V66&PCI frequency.
• Programmable output divider ratios.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system if system
malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input.
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• CPU - AGP skew < +/- 350ps
• AGP-PCI skew between 1~3.5ns
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
FS4 FS3 FS2 FS1 FS0
00000
00001
00010
00011
00100
00101
00110
00111
MHz
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
0 1 0 0 0 100.99
0 1 0 0 1 201.98
0 1 0 1 0 134.65
0 1 0 1 1 168.31
0 1 1 0 0 115.00
0 1 1 0 1 230.00
0 1 1 1 0 153.33
0 1 1 1 1 191.67
1 0 0 0 0 100.00
1 0 0 0 1 200.00
1 0 0 1 0 133.33
1 0 0 1 1 166.67
1 0 1 0 0 200.00
1 0 1 0 1 400.00
1 0 1 1 0 266.67
1 0 1 1 1 333.33
1 1 0 0 0 105.00
1 1 0 0 1 210.00
1 1 0 1 0 140.00
1 1 0 1 1 175.00
1 1 1 0 0 110.00
1 1 1 0 1 220.00
1 1 1 1 0 146.66
1 1 1 1 1 183.34
1236A—08/06/07
AGP
MHz
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
67.33
67.33
67.33
67.32
76.67
76.67
76.66
76.67
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
Pin Configuration
*FS1/REF0
**FS0/REF1
VDDREF
X1
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
VDDPCI
GND
**MODE/PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
GND
PCICLK5
PCICLK6
**FS3/48MHz
**Sel24_48#/24_48MHz
GND
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDA
47 GND
46 IREF
45 CPUCLKT_ITP/(PCI_STOP#)
44 CPUCLKC_ITP/(CPU_STOP#)
43 GND
42 CPUCLKT1
41 CPUCLKC1
40 VDDCPU
39 CPUCLKT0
38 CPUCLKC0
37 GND
36 25Mhz_0
35 25Mhz_1
34 VDD2.5
33 VttPWR_GD/PD#
32 SDATA
31 SCLK
30 Reset#
29 3V66_0
28 GND
27 VDD3V66
26 3V66_1
25 3V66_2
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
48-pin SSOP & TSSOP

1 page




ICS952906A pdf
Integrated
Circuit
Systems, Inc.
Table1: QuadRom Frequency Selection Table
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
Bit6 Bit5
FS4 FS3 FS2 FS1 FS0 MHz
AGP
MHz
PCI
MHz
0 0 0 0 0 0 0 100.00 66.67 33.33
0 0 0 0 0 0 1 200.00 66.67 33.33
0 0 0 0 0 1 0 133.33 66.67 33.33
0 0 0 0 0 1 1 166.67 66.67 33.33
0 0 0 0 1 0 0 200.00 66.67 33.33
0 0 0 0 1 0 1 400.00 66.67 33.33
www.DataSheet40U.com0 0 0 1 1 0 266.67 66.67 33.33
0 0 0 0 1 1 1 333.33 66.67 33.33
0 0 0 1 0 0 0 100.99 67.33 33.66
0 0 0 1 0 0 1 201.98 67.33 33.66
0 0 0 1 0 1 0 134.65 67.33 33.66
0 0 0 1 0 1 1 168.31 67.32 33.66
0 0 0 1 1 0 0 115.00 76.67 38.33
0 0 0 1 1 0 1 230.00 76.67 38.33
0 0 0 1 1 1 0 153.33 76.66 38.33
0 0 0 1 1 1 1 191.67 76.67 38.33
0 0 1 0 0 0 0 100.00 66.66 33.33
0 0 1 0 0 0 1 200.00 66.66 33.33
0 0 1 0 0 1 0 133.33 66.66 33.33
0 0 1 0 0 1 1 166.67 71.43 35.71
0 0 1 0 1 0 0 200.00 66.66 33.33
0 0 1 0 1 0 1 400.00 66.66 33.33
0 0 1 0 1 1 0 266.67 66.66 33.33
0 0 1 0 1 1 1 333.33 66.66 33.33
0 0 1 1 0 0 0 105.00 69.99 35.00
0 0 1 1 0 0 1 210.00 69.99 35.00
0 0 1 1 0 1 0 140.00 69.99 35.00
0 0 1 1 0 1 1 175.00 69.99 35.00
0 0 1 1 1 0 0 110.00 73.33 36.66
0 0 1 1 1 0 1 220.00 73.33 36.66
0 0 1 1 1 1 0 146.66 73.33 36.66
0 0 1 1 1 1 1 183.34 73.33 36.66
Spread
%
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0.25% Center
0.25% Center
0.25% Center
0.25% Center
No Spread
No Spread
No Spread
No Spread
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
ICS952906A
1236A—08/06/07
5

5 Page





ICS952906A arduino
Integrated
Circuit
Systems, Inc.
ICS952906A
I2C Table: Vendor & Revision ID Register
Byte 7
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
www.DataSheet4UB.icto0m
-
-
-
-
-
-
-
-
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
I2C Table: Byte Count Register
Byte 8
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control
Function
REVISION ID
VENDOR ID
Control
Function
Byte Count
Programming b(7:0)
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
I2C Table: Watchdog Timer Register
Byte 9
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
Control
Function
WD Timer Bit 7
WD Timer Bit 6
WD Timer Bit 5
WD Timer Bit 4
WD Timer Bit 3
WD Timer Bit 2
WD Timer Bit 1
WD Timer Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
01
These bits represent X*290ms the
watchdog timer waits before it goes to
alarm mode. Default is 11 x 293ms =
3.2s.
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Name
M/NEN
WDEN
WDFSEN
WD SF4
WD SF3
WD SF2
WD SF1
WD SF0
Control
Function
M/N Programming
Enable
Watchdog Enable
WD Safe Frequency
Mode
Watch Dog Safe Freq
Programming bits
Type
RW
R
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Latched FS/Byte0
1
Enable
Enable
WD B10 b(4:0)
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
PWD
X
X
X
X
0
0
0
1
PWD
0
0
0
0
1
1
1
1
PWD
0
0
0
0
1
0
1
1
PWD
0
0
0
0
0
0
0
0
1236A—08/06/07
11

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