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PDF A82DL1632T Data sheet ( Hoja de datos )

Número de pieza A82DL1632T
Descripción (A82DL16x2T) Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Fabricantes AMIC Technology 
Logotipo AMIC Technology Logotipo



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No Preview Available ! A82DL1632T Hoja de datos, Descripción, Manual

A82DL16x2T(U) Series
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM,
A82DL16x2T(U) 16 Megabit (2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only,
Simultaneous Operation Flash Memory and 2M (128Kx16 Bit) Static RAM
Preliminary
www.DataSheet4U.com
Document Title
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82DL16x2T(U) 16 Megabit
(2Mx8 Bit/1Mx16 Bit) CMOS 3.3 Volt-only, Simultaneous Operation Flash Memory and 2M
(128Kx16 Bit) Static RAM
Revision History
Rev. No.
0.0
0.1
History
Initial issue
Update Figure 23
Issue Date
March 25, 2005
May 17, 2005
Remark
Preliminary
PRELIMINARY (May, 2005, Version 0.1)
AMIC Technology, Corp.

1 page




A82DL1632T pdf
Product Information Guide
Part Number
Speed Options
Standard Voltage Range:
VCC_F/VCC_S=2.7-3.6V
Max Access Time (ns)
CE_F / CE_S Access (ns)
OE Access (ns)
MCP Block Diagram
A82DL16x2T(U) Series
A82DL16x2T(U)
70
70
70
40
www.DataSheet4U.com
A19 to A0
BYTE_F
WP/ACC
CE_F
RESET
A19 to A0
VCC_F
VSS
RY/BY
16M Bit
Flash Memory
I/O15 (A-1) to I/O0
VCC_S
VSS
WE
OE
LB_S
UB_S
CE1_S
CE2_S
A16 to A0
2M Bit
Static RAM
I/O15 (A-1) to I/O0
I/O15 (A-1) to I/O0
PRELIMINARY (May, 2005, Version 0.1)
4
AMIC Technology, Corp.

5 Page





A82DL1632T arduino
A82DL16x2T(U) Series
Word/Byte Configuration
The BYTE_F pin determines whether the I/O pins I/O15-I/O0
operate in the byte or word configuration. If the BYTE_F pin
is set at logic ”1”, the device is in word configuration, I/O15-
I/O0 are active and controlled by CE_F and OE .
If the BYTE_F pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled by
CE_F and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is
used as an input for the LSB(A-1) address function.
www.DataShReeeqt4uUi.rceomments for Reading Array Data
To read array data from the outputs, the system must drive
the CE_F and OE pins to VIL. CE_F is the power control
and selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH. The
BYTE_F pin determines whether the device outputs array
data in words or bytes.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. Each bank
remains enabled for read access until the command register
contents are altered.
See "Requirements for Reading Array Data" for more
information. Refer to the AC Read-Only Operations table for
timing specifications and to Figure 11 for the timing
waveform, lCC1_F in the DC Characteristics table represents
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE_F to VIL, and
OE to VIH.
For program operations, the BYTE_F pin determines
whether the device accepts program data in bytes or words,
Refer to “Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word
or byte, instead of four. The “Word / Byte Program Command
Sequence” section has details on programming data to the
device using both standard and Unlock Bypass command
sequence.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables 3-4 indicate the
address range that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the
boot/parameter sectors, and Bank 2 contains the larger, code
sectors of uniform size. A “bank address” is the address bits
required to uniquely select a bank. Similarly, a “sector
address” is the address bits required to uniquely select a
sector.
ICC2_F in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through
the ACC function. This is one of two functions provided by
the WP /ACC pin. This function is primarily intended to allow
faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically
enters the aforementioned Unlock Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing VHH from the WP /ACC pin returns the
device to normal operation. Note that the WP /ACC pin must
not be at VHH for operations other than accelerated program-
ming, or device damage may result. In addition, the
WP /ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7-I/O0. Standard read
cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for more
information.
Simultaneous Read/Write Operations with Zero
Latency
This device is capable of reading data from one bank of
memory while programming or erasing in the other bank of
memory. An erase operation may also be suspended to read
from or program to another location within the same bank
(except the sector being erased). Figure 18 shows how read
and write cycles may be initiated for simultaneous operation
with zero latency. ICC6_F and ICC7_F in the DC Characteristics
table represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE
input.
The device enters the CMOS standby mode when the
CE_F & RESET pins are both held at VCC_F ± 0.3V. (Note
that this is a more restricted voltage range than VIH.) If
CE_F and RESET are held at VIH, but not within VCC_F ±
0.3V, the device will be in the standby mode, but the standby
current will be greater. The device requires the standard
access time (tCE) for read access when the device is in either
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3_F in the DC Characteristics tables represent the standby
current specification.
PRELIMINARY (May, 2005, Version 0.1)
10
AMIC Technology, Corp.

11 Page







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