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PDF 24LC08 Data sheet ( Hoja de datos )
| Número de pieza | 24LC08 | |
| Descripción | 8K-Bit Serial EEPROM | |
| Fabricantes | Ceramate Technical | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 24LC08 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
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24LC08
8K-Bit Serial EEPROM
OVERVIEW
The 24LC08 serial EEPROM has a 8,192-bit (1,024-byte) capacity, supporting the standard I 2CTM-bus
serial interface. It is fabricated using CERAMATE's most advanced CMOS technology. One of its major’feature
is a hardware-based write protection circuit for the entire memory area. Hardware-based write protection
is controlled by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to
16 bytes of data into the EEPROM in a single write operation. Another significant feature of the 24LC08
is its support for fast mode and standard mode.
FEATURES
www.DataSI2hCe-Beut4sUIn.ctoemrface
• Two-wire serial interface
• Automatic word address increment
EEPROM
• 8K-bit (1,024-byte)
storage area
• 16-byte page buffer
• Typical 3.5 ms write cycle time with
auto-erase function
• Hardware-based write protection for the entire
EEPROM (using the WP pin)
• EEPROM programming voltage generated
on chip
• 1,000,000 erase/write cycles
• 100 years data retention
ORDERING INFORMATION
Operating Characteristics
• Operating voltage
— 2.5 V to 5.5 V (write)
— 2.2 V to 5.5 V (read)
• Operating current
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 µA at 5.5 V
— Maximum stand-by current: < 5 µA at 3.3 V
• Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (industrial)
• Operating clock frequencies
— 100 kHz at standard mode
— 400 kHz at fast mode
• Electrostatic discharge (ESD)
— 3,000 V (HBM)
— 300 V (MM)
Packages
• 8-pin DIP, SOP, and TSSOP
24 LC 08 X X
Operating Voltage
LC:2.5~5.5V,CMOS
Type
08=8K
Temp. grade
Blank:-25~+70
Packing
Blank :Tube
A :Taping(SOP8)
T :Taping(TSSOP8)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Fax:886-3-3521052
Page 1 of 23
Email: [email protected]
Http: www.ceramate.com.tw
Rev 1.1 Nov.18, 2002
1 page  
24LC08
8K-Bit Serial EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The 24LC08 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of
a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to
V CC by a pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus
is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop
conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to two 24LC08 devices can be
connected to the same I2C-bus as slaves (see Figure 3-6). Both the master and slaves can operate as transmitter
www.Daotar Srehceeeivte4rU, .bcuotmthe master device determines which bus operating mode would be active.
SDA
SCL
Bus Master
(Transmitter/
Receiver)
MCU
Slave 1
24LC08
Tx/Rx
A0 A1 A2
To VCC or VSS
VCC VCC
RR
Slave 2
24LC08
Tx/Rx
A0 A1 A2
To VCC or VSS
NOTES:
1. The A0, A1 do not affect the device address of the 24LC08.
Figure 3-6. Typical Configuration (16 Kbits of Memory on the I2C-Bus)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Fax:886-3-3521052
Page 5 of 23
Email: [email protected]
Http: www.ceramate.com.tw
Rev 1.1 Nov.18, 2002
5 Page 
24LC08
8K-Bit Serial EEPROM
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the 24LC08 This method of write protection is
controlled by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored. The 24LC08
will acknowledge slave and word address, but it will not generate an acknowledge after receiving the first byte
of the data. Thus the write cycle will not be started when the stop condition is generated. By connecting the WP
pin to V SS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to prevent data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
www.DatatShheebeuts4,Ub.uctodmata bytes are not acknowledged.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the 24LC08 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends the eight
bits of data. The master does not acknowledge the transfer but it does generate a Stop condition. In this way,
the 24LC08 effectively stops the transmission (see Figure 3-12).
Start Slave Address
Data
Stop
AN
CO
K
A
C
K
Figure 3-12. Current Address Byte Read Operation
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Fax:886-3-3521052
Page 11 of 23
Email: [email protected]
Http: www.ceramate.com.tw
Rev 1.1 Nov.18, 2002
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet 24LC08.PDF ] | |
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