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PDF LM2657 Data sheet ( Hoja de datos )
| Número de pieza | LM2657 | |
| Descripción | Dual Synchronous Buck Regulator Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 2005
LM2657
Dual Synchronous Buck Regulator Controller
General Description
The LM2657 is an adjustable 200kHz-500kHz dual channel
voltage-mode controlled high-speed synchronous buck
regulator controller ideally suited for high current applica-
tions. The LM2657 requires only N-channel FETs for both
the upper and lower positions of each stage. It features line
feedforward to improve the response to input transients. At
very light loads, the user can choose between the high-
efficiency Pulse-skip mode or the constant frequency
Forced-PWM mode. Lossless current limiting without the use
of external sense resistors is made possible by sensing the
voltage drop across the bottom FET. A unique adaptive duty
cycle clamping technique is incorporated to significantly re-
duce peak currents under abnormal load conditions. The two
independently programmable outputs switch 180˚ out of
phase (interleaved switching) reducing the input capacitor
and filter requirements. The input voltage range is 4.5V to
28V while the output voltages are adjustable down to 0.6V.
Standard supervisory and control features include Soft-start,
Power Good, output Under-voltage and Over-voltage protec-
tion, Under-voltage Lockout, and chip Enable.
Features
n Input voltage range from 4.5V to 28V
n Synchronous dual-channel interleaved switching
n Forced-PWM or Pulse-skip modes
n Lossless bottom-side FET current sensing
n Adaptive duty cycle clamp
n High current N-channel FET drivers
n Low shutdown supply current
n Reference voltage accurate to within ±1.5%
n Output voltage adjustable down to 0.6V
n Power Good flag and Chip Enable
n Under-voltage lockout
n Over-voltage/Under-voltage protection
n Soft-start
n Switching frequency adjustable 200kHz-500kHz
n TSSOP-28 package
Applications
n Low Output Voltage High-Efficiency Buck Regulators
Typical Application (Channel 2 in parenthesis)
© 2005 National Semiconductor Corporation DS201347
20134704
www.national.com
1 page  
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Voltages from the indicated pins to GND unless otherwise
indicated (Note 2):
VIN -0.3V to 30V
V5 -0.3V to 7V
VDD
-0.3V to 7V
BOOT1, BOOT2
-0.3V to 36V
BOOT1 to SW1, BOOT2 to
SW2
-0.3V to 7V
SW1, SW2
-0.3V to 30V
ILIM1, ILIM2
-0.3V to 30V
SENSE1, SENSE2, FB1, FB2
-0.3V to 7V
PGOOD
-0.3V to 7V
EN
Junction Temperature
ESD Rating (Note 3)
Ambient Storage Temperature
Range
Soldering Dwell Time,
Temperature
Wave
Infrared
Vapor Phase
-0.3V to 7V
+150˚C
2kV
-65˚C to +150˚C
4 sec, 260˚C
10 sec, 240˚C
75 sec, 219˚C
Operating Ratings (Note 1)
VIN
VDD, V5
Junction Temperature
4.5V to 28V
4.5V to 5.5V
-40˚C to +125˚C
Electrical Characteristics
Specifications with standard typeface are for TJ = 25˚C, and those with boldface apply over full
Operating Junction Temperature range. VDD = V5 = 5V, VSGND = VPGND = 0V, VIN = 15V, VEN = 3V, RFADJ = 22.1kΩ un-
less otherwise stated (Note 4). Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Symbol
Parameter
Conditions
Typical
Min (Note Max
5)
Units
Reference
VFB
FB Pin Voltage at
VDD = 4.5V to 5.5V,
591 600 609 mV
Regualtion (either FB Pin) VIN = 4.5V to 28V
VFB_LINE REG
VFB Line Regulation (∆VFB) VDD = 4.5V to 5.5V,
VIN = 4.5V to 28V
0.5
IFB
Chip Supply
FB Pin Current (sourcing) VFB at regulation
20 100 nA
IQ_VIN
ISD_VIN
IQ_VDD
ISD_VDD
IQ_V5
ISD_V5
IQ_BOOT
ISD_BOOT
VDD_UVLO
VIN_UVLO
Logic
VIN Quiescent Current
VIN Shutdown Current
VDD Quiescent Current
VDD Shutdown Current
V5 Normal Operating
Current
V5 Shutdown Current
BOOT Quiescent Current
BOOT Shutdown Current
VDD UVLO Threshold
VDD UVLO Hysteresis
VIN UVLO Threshold
VIN UVLO Hysteresis
VFB1 = VFB2 = 0.7V
VEN = 0V
VFB1 = VFB2 = 0.7V
VEN = 0V
VFB1 = VFB2 = 0.7V
VFB1 = VFB2 = 0.5V
VEN = 0V
VFB1 = VFB2 = 0.7V
VFB1 = VFB2 = 0.5V
VEN = 0V
VDD rising up to VUVLO
VDD = V5 falling from VUVLO
VIN rising up to VUVLO
VIN falling from VUVLO
100 200
µA
0 5 µA
2.5 4 mA
6 15 µA
0.3 0.5 mA
1 1.5
0 5 µA
2 5 µA
300 500
1 5 µA
3.9 4.2 4.5
V
0.5 0.7 0.9
V
3.9 4.2 4.5
V
0.1 0.3
V
IEN
VEN_HI
EN Input Current
Minimum EN Input Logic
High
VEN = 0 to 5V
0
2
µA
V
VEN_LO
Maximum EN Input Logic
Low
0.8 V
RFPWM
FPWM Pull-down
VFPWM = 2V
100 200 1000 kΩ
5 www.national.com
5 Page 
Operation Descriptions (Continued)
In a conventional converter, as the load is decreased to
about 10-30% of maximum load current, DCM (Discontinu-
ous Conduction Mode) occurs. In this condition the inductor
current falls to zero during the OFF-time, and stays there
until the start of the next switching cycle. In this mode, if the
load is decreased further, the duty cycle decreases (pinches
off), and ultimately may decrease to the point where the
required pulse width becomes less than the minimum ON-
time achievable by the converter (controller + FETs). Then a
sort of random skipping behavior occurs as the error ampli-
fier struggles to maintain regulation. There are two ways to
prevent random pulse skipping from occuring.
One way is to keep the lower FET ON until the start of the
next cycle (as in the LM2657 operated in FPWM mode). This
allows the inductor current to drop to zero and then actually
reverse direction (negative direction through inductor, pass-
ing from drain to source of lower FET, see Channel 4 in
Figure 2). Now the current can continue to flow continuously
until the end of the switching cycle. This maintains CCM and
the duty cycle does not start to pinch off as in typical DCM.
Nor does it lead to the undesirable random skipping de-
scribed above. Note that the pulse width (duty cycle) for
CCM is virtually constant for any load and therefore does not
usually run into the minimum ON-time restriction. But it can
happen, especially when the application consists of a very
high input voltage, a low output voltage rail, and the switch-
ing frequency is set high. Let us check the LM2657 to rule
out this remote possibility. For example, with an input of 24V,
an output of 1V, the duty cycle is 1/24 = 4.2%. This leads to
a required ON-time of 0.042* 3.3µs = 0.14 µs at a switching
frequency of 300kHz (T=3.3 µs). Since 140ns exceeds the
minimum ON-time of 30ns of the LM2657, normal constant
frequency CCM mode of operation is assured in FPWM
mode at virtually any load.
The second way to prevent random pulse skipping in discon-
tinuous mode is the Pulse-skip (SKIP) Mode. In SKIP Mode,
a zero-cross detector at the SW pin turns off the bottom FET
when the inductor current decays to zero (actually at VSW-
_ZERO, see Electrical Characteristics table). This, however,
would still amount to conventional DCM, with its attendant
idiosyncrasies at extremely light loads as described earlier.
The LM2657 avoids the random skipping behavior and re-
places it with a more consistent SKIP mode. In conventional
DCM, a converter would try to reduce its duty cycle from the
CCM value as the load decreases, as explained previously.
So it would start with the CCM duty cycle value (at the
CCM-DCM boundary), but as the load decreases, the duty
cycle would try to shrink to zero. However, in the LM2657,
the DCM duty cycle is not allowed to fall below 85% of the
CCM value. So when the theoretically required DCM duty
cycle value falls below what the LM2657 is allowed to deliver
(in this mode), pulse-skipping starts. It will be seen that
several of these excess pulses may be delivered until the
output capacitors charge up enough to notify the error am-
plifier and cause its output to reverse. Thereafter, several
pulses could be skipped entirely until the output of the error
amplifier again reverses. The SKIP mode therefore leads to
a reduction in the average switching frequency. Switching
losses and FET driver losses, both of which are proportional
to frequency, are significantly reduced at very light loads and
efficiency is boosted. SKIP mode also reduces the circulat-
ing currents and energy associated with the FPWM mode.
See Figure 3 for a typical plot of SKIP mode at very light
loads. Note the bunching of several fixed-width pulses fol-
lowed by skipped pulses. The average frequency can actu-
ally fall very low at very light loads. When this happens the
inductor core is seeing only very mild flux excursions, and no
significant audible noise is created. But if EMI is a particu-
larly sensitive issue for the particular application, the user
can simply opt for the slightly less efficient, constant fre-
quency FPWM mode.
CH1: HDRV, CH2: LDRV, CH3: SW, CH4: IL (0.2A/div)
Output 1V @ 0.04A, VIN = 10V, SKIP, L = 10µH, f = 300kHz
20134711
FIGURE 3. Normal SKIP Mode Operation at Light
Loads
The SKIP mode is enabled when the FPWM pin is held low
(or left floating). At higher loads, and under steady state
conditions (above CCM-DCM boundary), there will be abso-
lutely no difference in the behavior of the LM2657 or the
associated converter waveforms based on the voltage ap-
plied on the FPWM pin. The differences show up only at light
loads.
Also, under startup, since the currents are high until the
output capacitors have charged up, there will be no observ-
able difference in the shape of the ramp-up of the output rails
in either SKIP mode or FPWM mode. The design has thus
forced the startup waveforms to be identical irrespective of
whether the FPWM mode or the SKIP mode has been
selected.
The designer must realize that even at zero load condition,
there is circulating current when operating in FPWM mode.
This is illustrated in Figure 4. Since duty cycle is the same as
for conventional CCM, from V = L* ∆I / ∆t it can be seen that
∆I (or Ipp in Figure 4) must remain constant for any load,
including zero. At zero load, the average current through the
inductor is zero, so the geometric center of the sawtooth
waveform (the center being always equal to load current) is
along the x-axis. At critical conduction (boundary between
conventional CCM and what should have been DCM were it
not in FPWM mode), the load current is equal to Ipp/2. Note
that excessively low values of inductance will produce much
higher current ripple and this will lead to higher circulating
currents and dissipation.
11 www.national.com
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet LM2657.PDF ] | |
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