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Número de pieza LM2645MTD
Descripción Advanced Two-Phase Switching Controller With Two Linear Outputs
Fabricantes National Semiconductor 
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No Preview Available ! LM2645MTD Hoja de datos, Descripción, Manual

April 2001
LM2645
Advanced Two-Phase Switching Controller With Two
Linear Outputs
General Description
The LM2645 is a feature-rich IC that combines two current
mode synchronous buck regulator controllers, an adjustable
linear regulator controller and a fixed 3.3V standby output
rail.
The two switching regulator controllers operate 180˚ out of
phase. This feature reduces the input ripple RMS current,
thereby significantly reducing the required input capacitance.
The two switching regulator outputs can also be paralleled to
operate as a dual-phase regulator.
The use of synchronous rectification and pulse-skip opera-
tion at light load achieves high efficiency over a wide load
range. Fixed-frequency operation can be obtained by dis-
abling the pulse-skip mode. The switching frequency of the
LM2645 is user selectable between 200 kHz or 300 kHz.
The first switching controller (Channel 1) features a fixed 5V
output, and the second switching controller controller (Chan-
nel 2) features a fixed 3.3V output. Both channels can also
be independently adjusted from 1.3 to 5.5V. The adjustable
linear regulator can be adjusted from 3.3V to 15V. An internal
5V rail is also available externally for driving bootstrap cir-
cuitry. This rail also serves as the input for an internal LDO
that provides the fixed 3.3V/50mA output rail.
Current-mode feedback control assures excellent line and
load regulation and a wide loop bandwidth for excellent
response to fast load transients. Current is sensed across
either the Vds of the top FET or across an external sense
resistor connected in series with the drain of the top FET.
Current limit is independently adjustable for each channel.
The analog soft-start for the switching controllers uses an
innovative new approach. It is independent of the input
voltage which makes the soft-start behavior more predict-
able and controllable.
Independant PGOOD signals monitor each of the switching
regulator outputs. The switching outputs have under-voltage
and over-voltage latch protection, while the output of the
external linear regulator has undervoltage latch protection.
The undervoltage latch can be disabled or adjustably de-
layed.
Features
GENERAL
n 4.5V to 30V input range
n Power good function
n Input under-voltage lockout
n 10 µA Shutdown/Recycle for entire chip
n Thermal shutdown
n TSSOP package
SWITCHING SECTION
n Two synchronous buck regulators for fixed 5V/3.3V or
adjustable outputs
n Outputs adjustable from 1.3V to 5.5V
n 0.04% (typical) line and load regulation error
n Selectable switching frequency 200/300 kHz
n Two channels operating 180˚ out of phase
n Separate on/off for each channel
n Separate Power Good signals
n Current mode control with or without sense resistor
n Adjustable cycle-by-cycle current limit
n Skip-mode operation available
n Negative current limit
n Separate soft start for each channel
n Output UVP and OVP
n Programmable output UVP delay
n Self discharge of output capacitors when turned off
LINEAR SECTION
n Adjustable (3.3V to 15V) linear regulator with external
PNP pass transistor
n ±2% initial tolerance of set voltage
n Output UVP for adjustable linear regulator
n Fixed 3.3V/50mA output rail
n Fixed 5V reference rail
Applications
n Notebook and sub-notebook computers
n Embedded computer systems
n Battery-powered instruments
n High end gaming systems
n Set-top boxes
n WebPAD
© 2001 National Semiconductor Corporation DS200159
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LM2645MTD arduino
Electrical Characteristics (Continued)
Unless otherwise specified, VIN = 15V, SGND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type ap-
ply over the entire operating junction temperature range, 0˚C to +125˚C. Specifications appearing in plain type are measured
using low duty cycle pulse testing with TA = 25˚C (Note 5), (Note 6). Min/Max limits are guaranteed by design, test, or statisti-
cal analysis.
Symbol
Parameter
Conditions
Min Typ Max Units
SYSTEM
IIL Maximum Input Leakage Logic Input Voltage 0 or 5V
Current (SD,
FPWM/2NDFB, ON1,
ON2, FSEL).
±0.1
µA
Logic Outputs
IOL
PGOOD Low Sink
VPGOOD = 0.4V
Current
1.4 mA
IOH PGOOD High Leakage VPGOOD = 5V
Current
50 200 nA
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the
device is guaranteed. For guaranteed performance limits and associated test conditions, see the Electrical Characteristic tables.
Note 2: Maximum allowable power dissipation is calculated by using PDMAX = (TJMAX - TA)/θJA, where TJMAX is the maximum junction temperature, TA is the
ambient temperature and θJA is the junction-to-ambient thermal resistance of the specified package. The 1.56W rating results from using 150˚C, 25˚C, and 80˚C/W
for TJMAX, TA, and θJA respectively. A θJA of 90˚C/W represents the worst-case condition of no heat sinking of the 48-pin TSSOP. Heat sinking allows the safe
dissipation of more power. The Absolute Maximum power dissipation should be derated by 12.5mW per ˚C above 25˚C ambient. The LM2645 actively limits its
junction temperature to about 150˚C.
Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook available from National Semiconductor Corporation.
Note 4: Except for SW1, SW2, CBOOT1 and CBOOT2 pins which are 1.5kV. For testing purposes, ESD was applied using the human-body model, a 100pF
capacitor discharged through a 1.5kresistor.
Note 5: A typical is the center of characterization data measured with low duty cycle pulse tsting at TA = 25˚C. Typicals are not guaranteed.
Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TA = TJ = 25˚C. All hot and cold limits
are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Note 7: Both switching controllers are OFF. The linear regulators VLIN5 and 3OUT remain ON.
Note 8: The output voltage at the VLIN5 pin may be as high as 6.5V in shutdown mode (SD 0.6V).
Note 9: When SS1, SS2 pins are charged above this voltage and either of the output voltage at VOUT1 or VOUT2 is still below the regulation limit, the under voltage
protection feature is initialized.
Note 10: Above this voltage, the under voltage protection is enabled.
Note 11: For each device, there is a 10% (typical) gap of the measured output voltage between the PGOOD signal transitions from high to low and the under voltage
protection is activated. The under voltage protection will not be activated while the PGOOD signal is in the logic HIGH state.
Note 12: During normal shutdown or UVP, LDRV1or LDRV2 pin goes high when VO1, VO2 detects an output voltage below this level.
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