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Número de pieza LM2636MTC
Descripción 5-Bit Programmable Synchronous Buck Regulator Controller
Fabricantes National Semiconductor 
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October 1999
LM2636
5-Bit Programmable Synchronous Buck Regulator
Controller
General Description
The LM2636 is a high speed controller designed specifically
for use in synchronous DC/DC buck converters for advance
d microprocessors. A 5-bit DAC accepts the VID code di-
rectly from the CPU and adjusts the output voltage from 1.3V
to 3.5V. It provides the power good, over-voltage protection,
and output enable features as required by Intel VRM speci-
fications. Current limiting is achieved by monitoring the volt-
age drop across the rDS_ON of the high side MOSFET, which
eliminates an expensive current sense resistor.
The LM2636 employs a fixed-frequency voltage mode PWM
architecture. To provide a faster response to a large and fast
load transient, two ultra-fast comparators are built in to moni-
tor the output voltage and override the primary control loop
when necessary. The PWM frequency is adjustable from 50
kHz to 1 MHz through an external resistor. The wide range of
PWM frequency gives the power supply designer the flexibil-
ity to make trade-offs between load transient response per-
formance, MOSFET cost and the overall efficiency. The
adaptive non-overlapping MOSFET gate drivers help avoid
any potential shoot-through problem while maintaining high
efficiency. BiCMOS gate drivers with rail-to-rail swing ensure
that no spurious turn-on occur. When only 5V is available, a
bootstrap structure can be employed to accommodate an
NMOS high side switch. The precision reference trimmed to
2.5% over temperature is available externally for use by
other regulators. Dynamic positioning of load voltage, which
helps cut the number of output capacitors, can also be imple-
mented easily.
Features
n 1.3V to 3.5V 5-bit programmable output voltage
n Synchronous rectification
n Power Good flag and output enable
n Over-voltage protection
n Initial Output Accuracy: 1.5% over temperature
n Current limit without external sense resistor
n Adaptive non-overlapping MOSFET gate drives
n Adjustable switching frequency: 50 kHz to 1 MHz
n Dynamic output voltage positioning
n 1.256V reference voltage available externally
n Plastic SO-20 package and TSSOP-20 package
Applications
n Motherboard power supply/VRM for Cyrix Gxm, Cyrix
Gxi, Cyrix MII, PentiumII, Pentium Pro, 6x86 and K6
processors
n 5V to 1.3V–3.5V high current power supplies
Typical Application
FIGURE 1. 5V to 1.3V–3.5V, 14A Power Supply
Pentiumis a trademark of Intel Corporation.
© 1999 National Semiconductor Corporation DS100834
DS100834-1
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LM2636MTC pdf
Electrical Characteristics (Continued)
VCC = 5V unless otherwise indicated under the Conditions column. Typicals and limits appearing in plain type apply for TA =
TJ = +25˚C. Limits appearing in boldface type apply over 0˚C to +70˚C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VOUTEN_IH
OUTEN Pin Input Logic
Low to Logic High Trip
Point
OUTEN Voltage
3.5 3.0
V
VOUTEN_IL
OUTEN Pin Input Logic
High to Logic Low Trip
Point
OUTEN Voltage
1.8 1.5
V
VREF
VREF_LOAD
Band Gap Reference
Reference Voltage at
Full Load
IVREF = 0 mA
IVREF = 0.5 mA, Sourcing
1.225
1.223
1.256
1.254
1.287
1.285
V
V
VREF_525
Reference Voltage at
High Line
IVREF = 0 mA, VCC = 5.25V
1.226
1.257
1.288
V
VREF_475
Reference Voltage at
Low Line
IVREF = 0 mA, VCC = 4.75V
1.224
1.255
1.286
V
VREF_LOAD Reference Voltage
Load Regulation
IVREF = 0.5 mA, Sourcing
−2 mV
VREF_LINE
Reference Voltage Line
Regulation
IVREF = 0 mA, VCC Changes from
5.25V to 4.75V
−0.5
mV
VSAWL
Ramp Signal Valley
Voltage
1.25 V
VSAWH
Ramp Signal Peak
Voltage
3.25 V
VPWRBAD_GD
PWRGD Pin Trip
Points (see Pin
Description for Pin 13)
% above DAC Output Voltage, when
Output Voltage
% below DAC Output Voltage, when
Output Voltage
10
−10
%
VPWRGD_BAD
PWRGD Pin Trip
Points (see Pin
Description for Pin 13)
% above DAC Output Voltage, when
Output Voltage
% below DAC Output Voltage, when
Output Voltage
8
−8
%
VOVP
Over-voltage Protection % above DAC Output Voltage
Trip Point
15 %
tPWRGD
tPWRBAD
Power Good Response
Time
Power Not Good
Response Time
VSENSE Rises from 0V to Rated
VOUT
VSENSE Falls from Rated VOUT to 0V
2
2
6 15 µs
6 15 µs
IOUTEN
OUTEN Pin Internal
Pull-Up Current
60 90 130 µA
VVID_IH
VID Pins Logic High
Trip Point
3.5 3.0
V
VVID_IL
VID Pins Logic Low
Trip Point
1.8 1.3
V
IVID VID0:4 Internal Pull-Up
Current
60 90 130 µA
tSS Soft Start Duration
2048
clock
cycles
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are conditions under which
the device operates correctly. Recommended Operating Conditions do not imply guaranteed performance limits.
Note 2: Maximum allowable DC power dissipation is a function of the maximum junction temperature, TJMAX , the junction-to-ambient thermal resistance, θJA, and
the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using:
The junction-to-ambient thermal resistance, θJA, for LM2636 in the M20B package is 88˚C/W, and 120˚C/W for the MTC20 package.
5
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LM2636MTC arduino
Applications Information (Continued)
sient. In the case of Pentium II power supply, fast recovery of
the load voltage from transient window back to the steady
state window is considered important. This limits the highest
inductance value that can be used. The lowest inductance
value is limited by the highest switching frequency that can
be practically employed. As the switching frequency in-
creases, the switching loss in the MOSFETs tends to in-
crease, resulting in less converter efficiency and larger heat
sinks. A good switching frequency is probably a frequency
under which the MOSFET conduction loss is higher than the
switching loss because the cost of the MOSFET is directly
related to its RDSON. The inductor size can be determined by
the following equation:
where VO_RIP is the peak-to-peak output ripple voltage, f is
the switching frequency. For commonly used low RDSON
MOSFETs, a reasonable switching frequency is 300 kHz. As-
sume an output peak-peak ripple voltage of 18 mV is to be
guaranteed, the total output capacitor ESR is 9 m, the input
voltage is 5V, and output voltage is 2.8V. The inductance
value according to the above equation will then be 2 µH. The
highest slew rate of the inductor current when the load
changes from no load to full load can be determined as fol-
lows:
where (di/dt)MAX is the maximum allowable input current
slew rate, which is 0.1A/µs in the case of the Pentium II
power supply. So the input inductor size, according to the
above equation, should be 2.1 µH.
DYNAMIC POSITIONING OF LOAD VOLTAGE
Since the Intel VRM specifications have defined two operat-
ing windows for the MPU core voltage, one being the steady
state window and the other the transient window, it is a good
idea to dynamically position the steady state output voltage
in the steady state window with respect to load current level
so that the output voltage has more headroom for load tran-
sient response. This requires information about the load cur-
rent. There are at least two simple ways to implement this
idea with LM2636. One is to utilize the output inductor DC re-
sistance, see Figure 7. The average voltage across the out-
put inductor is actually that across its DC resistance. That
average voltage is proportional to load current.
Since the switching node voltage VA bounces between the
input voltage and ground at the switching frequency, it is im-
possible to choose point A as the feedback point, otherwise
the dynamic performance will suffer and the system may
have some noise problems. Using a low pass filter network
around the inductor, such as the one shown in the figure,
seems to be a good idea. The feedback point is C.
where DMAX is the maximum allowed duty cycle, which is
around 0.9 for LM2636. For a load transient from 0A to 14A,
the highest current slew rate of the inductor, according to the
above equation, is 0.85A/µs, and therefore the shortest pos-
sible total recovery time is 14A/(0.85A/µs) = 16.5 µs. Notice
that the output voltage starts to recover whenever the induc-
tor starts to supply current.
The highest slew rate of the inductor current when the load
changes from full load to no load can be determined from the
same equation, but use DMIN instead of DMAX.
Since the DMIN of LM2636 at 300 kHz is 0%, the slew rate is
therefore −1.4A/µs. So the approximate total recovery time
will be 14A/(1.4A/µs) = 10 µs.
The input inductor is for limiting the input current slew rate
during a load transient. In the case that low ESR aluminum
electrolytic capacitors are used for the input capacitor bank,
voltage change due to capacitor charging/discharging is usu-
ally negligible for the first 20 µs. ESR is by far the dominant
factor in determining the amount of capacitor voltage
undershoot/overshoot due to load transient. So the worst
case is when the load changes between no load and full
load, under which condition the input inductor sees the high-
est voltage change across the input capacitors. Assume the
input capacitor bank is made up of three 16MV820GX, i.e.,
the total ESR is 15 m. Whenever there is a sudden load
current change, it has to initially be supported by the input
capacitor bank instead of the input inductor. So for a full load
swing between 0A and 14A, the voltage seen by the input in-
ductor is V = 14A x 15 m= 210 mV. Use the following
equation to determine the minimum inductance value:
DS100834-26
FIGURE 7. Dynamic Voltage Positioning by Utilizing
Output Inductor DC Resistance
Since at the switching frequency the impedance of the 0.1
µF is much less than 5 k, the bouncing voltage at point A
will be mainly applied across the resistor 5 k, and point C
will be much quieter than A. However, VCB average is still the
majority of VAB average, because of the resistor divider. So
in steady state VC = IO x rL + VCORE, where rL is the inductor
DC resistance. So at no load, output voltage is equal to VC,
and at full load, output voltage is IO x rL lower than VC. To fur-
ther utilize the steady state window, a resistor can be con-
nected between the FB pin and ground to increase the no
load output voltage to close to the upper limit of the window.
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