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PDF UDA1351H Data sheet ( Hoja de datos )
| Número de pieza | UDA1351H | |
| Descripción | 96 kHz IEC 958 audio DAC | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
www.DataSheet4U.com
UDA1351H
96 kHz IEC 958 audio DAC
Preliminary specification
File under Integrated Circuits, IC01
2000 Feb 18
1 page  
Philips Semiconductors
96 kHz IEC 958 audio DAC
Preliminary specification
UDA1351H
5 ORDERING INFORMATION
TYPE
NUMBER
UDA1351H
NAME
QFP44
PACKAGE
DESCRIPTION
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
www.DataSheet4U.com
6 BLOCK DIAGRAM
VERSION
SOT307-2
CLKOUT
TC TEST2 RTCB
VSSA VDDA
VDDA(DAC)
Vref
VOUTL VSSA(DAC) VOUTR
VDDA(PLL)
VSSA(PLL)
TEST1
32
31
34
29
CLOCK
AND
TIMING CIRCUIT
23 39 44
26 27
18 17 25 24 22
DAC
DAC
VDDD(C)
VSSD(C)
L3MODE
L3CLOCK
L3DATA
SELSTATIC
SPDIF0
SPDIF1
2
4
10
6
5
35
15
16
L3
INTERFACE
SLICER
IEC 958
DECODER
UDA1351H
DATA
OUTPUT
INTERFACE
NOISE SHAPER
INTERPOLATOR
AUDIO FEATURE PROCESSOR 12 MUTE
DATA
INPUT
INTERFACE
1 RESET
SELCHAN
13
VDDD
VSSD
43
3
11, 14,
28, 38,
40, 41
21 30 42
33 37 36 7 8 9
19 20
MGL976
n.c.
PREEM1
BCKO WSO DATAO BCKI SELCLK
LOCK PREEM0
DATAI WSI SELSPDIF
2000 Feb 18
Fig.1 Block diagram.
5
5 Page 
Philips Semiconductors
96 kHz IEC 958 audio DAC
Preliminary specification
UDA1351H
8.4 Auto mute
By default the outputs of the digital data output interface
and the DAC will be muted until the IC is locked,
regardless the level on pin MUTE (in static mode) or the
state of bit MT of the sound feature register (in L3 mode).
In this way only valid data will be passed to the outputs.
This mute is done in the SPDIF interface and is a hard
www.DataShemetu4Ute.c, onmot a cosine roll-off mute.
If needed this muting can be bypassed by setting
bit AutoMT to logic 0 via the L3 interface. As a result the IC
will no longer mute during out-of-lock situations.
8.5 Data path
The UDA1351H data path consists of the slicer and the
IEC 958 decoder, the digital data output and input
interfaces, the audio feature processor, digital interpolator
and noise shaper and the digital-to-analog converters.
8.5.1 IEC 958 INPUT
The UDA1351H IEC 958 decoder can select 1 out of 2
IEC 958 input channels. An on-chip amplifier with
hysteresis amplifies the IEC 958 input signal to CMOS
level (see Fig.4).
The extracted key parameters are:
• Pre-emphasis
• Audio sample frequency
• Two-channel PCM indicator
• Clock accuracy.
Both the lock indicator and the key channel status bits are
accessible via the L3 interface.
The UDA1351H supports the following sample
frequencies and data bit rates:
• fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s
• fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s
• fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s
• fs = 64.0 kHz, resulting in a data rate of 4.096 Mbits/s
• fs = 88.2 kHz, resulting in a data rate of 5.6448 Mbits/s
• fs = 96.0 kHz, resulting in a data rate of 6.144 Mbits/s.
The UDA1351H supports timing level I, II and III as
specified by the IEC 958 standard.
handbook, halfpage
75 Ω
10 nF
SPDIF0, 15,
SPDIF1 16
180 pF
UDA1351H
MGL975
Fig.4 IEC 958 input circuit and typical application.
All 24 bits of data for left and right are extracted from the
input bitstream as well as several of the IEC 958 key
channel-status bits.
2000 Feb 18
11
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| PDF Descargar | [ Datasheet UDA1351H.PDF ] | |
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