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PDF CY-62146DV30 Data sheet ( Hoja de datos )

Número de pieza CY-62146DV30
Descripción 4-Mbit (256K x 16) Static RAM
Fabricantes Cypress 
Logotipo Cypress Logotipo



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No Preview Available ! CY-62146DV30 Hoja de datos, Descripción, Manual

CY62146DV30
4-Mbit (256K x 16) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62146CV30
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = fmax
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA and 44-pin TSOPII
• Also available in Lead-free packages
Functional Description[1]
The CY62146DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has
Logic Block Diagram
AA190
A8
A7
A6
A5
A4
A3
A2
AA01
DATA IN DRIVERS
256K x 16
RAM Array
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O0 through
I/O15) are placed in a high-impedance state when: deselected
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A17). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62146DV30 is available in a 48-ball VFBGA, 44-pin
TSOPII packages.
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05339 Rev. *A
Revised February 2, 2005
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CY-62146DV30 pdf
CY62146DV30
Switching Characteristics Over the Operating Range [12]
45 ns[10]
55 ns
70 ns
Parameter
Description
Min. Max. Min.
Max.
Min. Max. Unit
Read Cycle
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to LOW Z[13]
OE HIGH to High Z[13, 14]
CE LOW to Low Z[13]
CE HIGH to High Z[13, 14]
tPU CE LOW to Power-Up
tPD CE HIGH to Power-Down
tDBE
BLE/BHE LOW to Data Valid
tLZBE
BLE/BHE LOW to Low Z[13]
tHZBE
BLE/BHE HIGH to HIGH Z[13, 14]
Write Cycle[15]
45 55
70 ns
45 55 70 ns
10 10
10 ns
45 55 70 ns
25 25 35 ns
55
5 ns
15 20 25 ns
10 10
10 ns
20 20 25 ns
00
0 ns
45 55 70 ns
25 25 35 ns
10 10
10 ns
15 20 25 ns
tWC Write Cycle Time
45 55
70 ns
tSCE CE LOW to Write End
40 40
60 ns
tAW Address Set-up to Write End
40
40
60 ns
tHA Address Hold from Write End
0
0
0 ns
tSA Address Set-up to Write Start
0
0
0 ns
tPWE
WE Pulse Width
35 40
45 ns
tBW BLE/BHE LOW to Write End
40
40
60 ns
tSD Data Set-up to Write End
25 25
30 ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High-Z[13, 14]
WE HIGH to Low-Z[13]
00
0 ns
15 20 25 ns
10 10
10 ns
Notes:
12.
Test conditions for all parameters other than three-state
input pulse levels of 0 to VCC(typ.), and output loading of
parameters assume signal transition time
the specified IOL/IOH as shown in the “AC
of 3 ns (1V/ns) or less, timing reference
Test Loads and Waveforms” section.
levels
of
VCC(typ)/2,
13.
At any given temperature
given device.
and
voltage
condition,
tHZCE
is
less
than
tLZCE,
tHZBE
is
less
than
tLZBE,
tHZOE
is
less
than
tLZOE,
and
tHZWE
is
less
than
tLZWE
for
any
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedence state.
15.
The internal Write time of the memory is
of these signals can terminate a write by
dgeofiningedINbAyCtTheIVoEv.eTrhlaepdoaftWa iEn,pCutEs=et-VuIpL,aBnHdEhoalnddt/iomriBngLEsh=ouVlIdL.bAellrseifgenreanlscemdutsot
be ACTIVE
the edge of
to initiate a write and any
the signal that terminates
the write.
Document #: 38-05339 Rev. *A
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CY-62146DV30 arduino
CY62146DV30
Document History Page
Document Title:CY62146DV30 MoBL® 4-Mbit (256K x 16) Static RAM
Document Number: 38-05339
REV.
Orig. of
ECN NO. Issue Date Change
Description of Change
**
213251 See ECN
AJU New Data Sheet
*A
316039 See ECN
PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables
Added Footnote #10 on page #4
Added Pb-free package ordering information on page # 9
Changed 44-lead TSOP-II package name on page 10 from Z44 to ZS44
Standardized Icc values across ‘L’ and ‘LL’ bins
Document #: 38-05339 Rev. *A
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