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PDF 74HC76 Data sheet ( Hoja de datos )
| Número de pieza | 74HC76 | |
| Descripción | DUAL J-K FLIP FLOP | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M74HC76
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
s HIGH SPEED :
fMAX = 67MHz (TYP.) at VCC = 6V
s LOW POWER DISSIPATION:
www.DataSheet4U.comICC =2µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s WIDE OPERATING VOLTAGE RANGE:
VCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 76
DESCRIPTION
The M74HC76 is an high speed CMOS DUAL J-K
FLIP FLOP WITH CLEAR fabricated with silicon
gate C2MOS technology.
Depending on with the logic level at J and K
inputs, this device changes state on the negative
going transition of clock pulse (CK). CLEAR (CLR)
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC76B1R
M74HC76M1R
T&R
M74HC76RM13TR
M74HC76TTR
and PRESET (PR) are independent of the clock
and are accomplished by a logic low on the
corresponding input.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
August 2001
1/11
1 page  
M74HC76
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Value
Symbol
Parameter
VCC
(V)
tTLH tTHL Output Transition
Time
tPLH tPHL Propagation Delay
www.DataSheet4U.com
Time (CK - Q, Q)
tPLH tPHL Propagation Delay
Time (CLR, PR -
Q, Q)
fMAX Maximum Clock
Frequency
tW(H)
tW(L)
Minimum Pulse
Width (CK)
tW(L) Minimum Pulse
Width (CLR, PR)
ts Minimum Set-up
Time
th Minimum Hold
Time
tREM Minimum Removal
Time (CLR, PR)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min.
6.2
31
37
Typ. Max.
30 75
8 15
7 13
60 125
15 25
13 21
76 140
18 28
16 24
21
63
67
18 75
6 15
6 13
22 75
6 15
6 13
25 75
7 15
6 13
0
0
0
20 75
6 15
5 13
Min.
5.0
25
30
Max.
95
19
16
155
31
26
175
35
30
95
19
16
95
19
16
95
19
16
0
0
0
95
19
16
Min.
4.2
21
25
Max.
110
22
19
190
38
32
210
42
36
ns
ns
ns
MHz
110
22 ns
19
110
22 ns
19
110
22 ns
19
0
0 ns
0
110
22 ns
19
CAPACITIVE CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 5.0
5 10 10 10 pF
CPD Power Dissipation
Capacitance (note 5.0
1)
38
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per FLIP/
FLOP)
5/11
5 Page 
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M74HC76
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom
© http://www.st.com
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74HC76.PDF ] | |
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