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PDF Y27US08121M Data sheet ( Hoja de datos )
| Número de pieza | Y27US08121M | |
| Descripción | HY27US08121M | |
| Fabricantes | Hynix Semiconductor | |
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HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory
Revision History
w w w . D a t a S h eNeot .4 U . c o m
0.0 Initial Draft
History
0.1 Renewal Product Group
0.2 Make a decision of PKG information
0.3 Append 1.8V Operation Product to Data sheet
1) Add Errata
Draft Date
Sep.17.2003
Oct.07.2003
Nov.08.2003
Dec.01.2003
Remark
Preliminary
Preliminary
Preliminary
Preliminary
tWC tWH tWP tRC tREH tRP tREA@ID Read
Specification 50 15 25 50 15 30
35
Relaxed value 60 20 40 60 20 40
45
0.4 Mar.28.2004
Preliminary
2) Modify the description of Device Operations
- /CE Don’t Care Enabled(Disabled) -> Sequential Row Read Disabled
(Enabled) (Page22)
3) Add the description of System Interface Using CE don’t care
(Page37)
1) Delete Errata
2) Change Characteristics (3V Product)
0.5 Before
After
tCRY
60 + tr
70 + tr
tREA@ID Read
35
45
Jun. 01. 2004 Preliminary
3) Delete Cache Program
1) Change TSOP1, WSOP1, FBGA package dimension
0.6 2) Edit TSOP1, WSOP1 package figures
3) Change FBGA package figure
Oct. 20. 2004
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.6 / Oct. 2004
1
1 page  
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
NC
NC
NC
NC
NC
NC
RB
RE
CE
NC
www.DataSheet4U.coNmC
Vcc
Vss
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1 48
11 23
NAND Flash
(x8)
33 76
24 25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
Vcc
Vss
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RB
RE
CE
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1 48
11 23
NAND Flash
(x16)
33 76
24 25
Figure 3. 48-TSOP1 Contactions, x8 and x16 Device
Vss
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
NC
NC
Vcc
NC
NC
NC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
Vss
Rev 0.6 / Oct. 2004
NC 1
NC
48
DU
NC
NC
NC
RB
RE
CE
DU NAND Flash
NC
Vcc
12
WSOP1
37
Vss 13
(x8)
36
NC
DU
CLE
ALE
WE
WP
NC
NC
DU
NC
NC 24
25
NC
NC
DU
NC
I/O7
I/O6
I/O5
I/O4
NC
DU
NC
Vcc
Vss
NC
DU
NC
I/O3
I/O2
I/O1
I/O0
NC
DU
NC
NC
Figure 4. 48-WSOP1 Contactions, x8 Device
5
5 Page 
HY27SS(08/16)121M Series
HY27US(08/16)121M Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Table 2. Bus Operation
BUS Operation
Command Input
Address Input
Data Input
www.DataSheet4U.cDoamta Output
Write Protect
Standby
CE
VIL
VIL
VIL
VIL
X
VIH
ALE
VIL
VIH
VIL
VIL
X
X
CLE RE WE WP
VIH
VIH
Rising
X(2)
VIL
VIH Rising
X
VIL
VIH Rising
X
VIL
Falling
VIH
X
X X X VIL
X X XX
I/O0 - I/O7
Command
Address
Data Input
Data Output
X
X
I/O8 - I/O15(1)
X
X
Data Input
Data Output
X
X
Note : (1) Only for x16 devices.
(2) WP must be VIH when issuing a program or erase command.
Table 3: Address Insertion, x8 Devices
Bus Cycle
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
I/O7
A7
A16
A24
VIL
I/O6
A6
A15
A23
VIL
I/O5
A5
A14
A22
VIL
I/O4
A4
A13
A21
VIL
I/O3
A3
A12
A20
VIL
I/O2
A2
A11
A19
VIL
I/O1
A1
A10
A18
VIL
I/O0
A0
A9
A17
A25
Note: (1). A8 is set Low or High by the 00h or 01h Command, see Pointer Operations section.
(2). Any address input cycles will be ignored with tALS > 0ns.
Table4: Address Insertion, x16 Devices
Bus Cycle
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
I/O8-I/
O15
X
X
X
VIL
I/O7
A7
A16
A24
VIL
I/O6
A6
A15
A23
VIL
I/O5
A5
A14
A22
VIL
Note: (1). A8 is Don't Care in x16 devices.
(2). Any address input cycles will be ignored with tALS > 0ns.
(3). A1 is the Least Significant Address for x16 devices.
(4). The 01h Command is not used in x16 devices.
I/O4
A4
A13
A21
VIL
I/O3
A3
A12
A20
VIL
I/O2
A2
A11
A19
VIL
I/O1
A1
A10
A18
VIL
I/O0
A0
A9
A17
A25
Rev 0.6 / Oct. 2004
11
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