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PDF DD-03296 Data sheet ( Hoja de datos )

Número de pieza DD-03296
Descripción 96-Channel Discrete to Digital Interface
Fabricantes DDC 
Logotipo DDC Logotipo



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No Preview Available ! DD-03296 Hoja de datos, Descripción, Manual

DD-03296
96-CHANNEL DISCRETE-TO-DIGITAL
INTERFACE
DESCRIPTION
APPLICATIONS
The DD-03296 device is a 96-channel
discrete-to-digital interface with uni-
versal HlRF-isolated inputs that
www.DataSheaect4cUep.cto2m8 V/Open, Open/Gnd and 28
V/Gnd signals.
The output is an addressable 8- or
16-bit tri-state port, selectable for
channel data, status, bounce, built-in
self-test (BIST) and major fault, and is
compatible with TTL logic.
The DD-03296 is specifically
designed to address built-in self-test
autonomy, fault isolation and toler-
ance.
Because of its high reliability and low
cost, these features enable the DD-
03296 to satisfy a variety of interface
requirements in aerospace applica-
tions, including flight critical, essen-
tial, and nonessential functions.
FEATURES
HIRF Layer
Universal Inputs
28 V/Gnd
Open/Gnd
28 V/Open
Built-in Self-Test
Soft Failure Reporting
Higher MTBUR
ARINC 429 Output Port
REFERENCE
INPUT
REFERENCE INPUT
DATA
BOUNCE
96
96
DISCRETE
INPUTS
PROCESSOR AND
TEST MATRIX
BIT
FAULT
96
96
96
SHIFT H/L TEST
MATRIX
ENABLE HI
5
TRANSFER DISCRETE ENABLE LO
5
33
ADDRESS DISCRETE DATA EN
DECODER ARINC DATA EN
SEL0
SEL1
SEL2
1 MHZ
RESET*
DUAL REDUNDANT
CLOCK AND
CONTROL LOGIC
ENABLE*
ADDRESS (A5..A0)
8/16 BUS
ARINC 429 DATA RATE
ARINC 429 MESSAGE RATE
DISCRETE
TRI-STATE
DRIVERS
16
DATA BUS
DATA (8/16 BITS)
DISCRETE
DATA
TRANSFER
VERIFIER
ARINC
DATA
TRANSFER
VERIFIER
TRANSFER FAULT
96 FAULT
96 BIT
TRANSFER FAULT
FAULT
PROCESSING
CIRCUITRY
DISCRETE
FAULT
ARINC
FAULT
FAULT*
ARINC 429
TRI-STATE
DRIVERS
16 DATA BUS
TRI-STATE ENABLES
READY
10µS CLOCK
80µS CLOCK
ARINC 429
XMITTER
(TTL)
2 ARINC 429
OUTPUT
NOTE: (*) Indicates active low.
© 1993, 1999 Data Device Corporation
U.S. Patent No. 5526288
FIGURE 1. DD-03296 BLOCK DIAGRAM
DATA READY

1 page




DD-03296 pdf
crete appropriate to its characteristic performance. See
BOUNCE on page 2.
ENABLE: (Pin 147) The ENABLE line controls the tri-state dri-
vers of the 8- or 16-bit Data Bus outputs. The tri-state Data Bus
drivers are enabled when this signal is a logic “0,” and are tri-
stated when this signal is a logic “1.” ENABLE is a read signal
and should only be low during read cycles.
8 /16 BITS: (Pin 104) A logic “0” selects the 16-bit data bus out-
put and a logic “1” selects the 8-bit data bus output.
ADDRESS LINES (A5...A0): (Pins 139, 140 and 143-146) The
www.DataShseixet4aUdd.croemss lines (A5... A0, where A0 is the LSB) provide for the
selection of the desired 8- or 16-bit Data Bus information in
accordance with TABLE 3 and TABLE 4 (Word/Byte Modes).
CLOCK (1MHZ CLK): (Pin 28) The user must supply a 1 MHz
clock whose stability is of no importance except to the serial bit
rate of the ARINC 429 port (see Note 1 of TABLE 1). The clock
is brought into the internal ASIC at two widely separated points
designated as CLOCK_A (primary) and CLOCK_B (secondary)
path.
The primary clock path will be selected and drive the device
unless a primary clock path fault is detected, in which case the
operation of the device will get switched over to the secondary
clock path.
Both clock paths are continually monitored for status and this
information is available as separate bits in the Status Register.
FACTORY TEST INPUTS: (Pins 39, 40, 149 and 150) The
TMUX, TMODE, FMUX and FMODE input signals are used for
factory testing and should be tied to logic “1” for the device to
operate properly.
RESET: (Pin 41) The RESET signal is used to reset the device
during factory testing. It may be connected to an external RC
network to provide a Power-on-Reset for the device. Under nor-
mal operating conditions this pin should be a no-connect. If there
is some reason to reset the device from external circuitry this pin
can be momentarily pulled to logic “0” through an open collector
device. Do not hard wire this pin to +5V or ground.
OUTPUTS
DATA (D15...D0): (Pins 123-138) 8-bit byte or 16-bit byte word
information is available on the Data Bus depending on the logic
state of the Bus Select line as described above.
In the Byte mode the upper and lower bytes are enabled sepa-
rately so that bit 0 can be hard-wired to bit 8, bit 1 to bit 9 etc.,
thereby providing an 8-bit data bus.
It is important that the 8-bit mode be selected if these data bits
are wired together or corrupted data will result. The available
data can be found under the Address Lines section found on
page 5.
FAULT: (Pin 148) The FAULT flag was designed to serve as an
interrupt to the microprocessor when a HARD error has been
detected within the device (See Note 2 of TABLES 3 and 4). If this
CHANNEL N
INPUT
REF A
TRIM A
600k
60k
93.3k
.01 µf
1.0k
COMPARATOR
-
+
OUTPUT TO LOGIC
TO OTHER COMPARATORS
5.72k
.1 µf
IDENTICAL REFERENCE
STRUCTURE
FOR REF B AND REF C
FIGURE 4. DD-03296 INPUT STRUCTURE
5

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DD-03296 arduino
DD-03182 LINE DRIVER PIN DESCRIPTIONS
See FIGURES 8, 9 and 10 for reference.
VREF (Input) – the voltage on VREF sets the output voltage levels
on AOUT and BOUT. The output logic level swings between +VREF
volts, 0 volts and -VREF volts.
N/C – No Connection
SYNC (Input) – Logic 0 will force outputs to NULL or MARK
state. Logic 1 enables data transmission.
CLOCK (Input) – Logic 0 will force outputs to NULL or MARK
state. Logic 1 enables data transmission.
DATA(A)/DATA(B) (Inputs) – Signals containing the serial data
www.DataShtoeebt4eUt.rcaonmsmitted on the ARINC 429 data bus.
CA/CB (Analog) – External timing capacitors are tied from these
points to ground to establish the output signal slew rate.
Typically, CA = CB = 75 pF for 100 kHz data and CA = CB = 500 pF
for 12.5 kHz data.
AOUT/BOUT (Outputs) – Line driver outputs which are connected to
the aircraft serial data bus.
-V (Input) – Negative supply input (-15 VDC nominal).
GND – Ground.
+V (Input) – Positive supply input (+15 VDC nominal).
V1 (Input) – Logic supply input (+5 VDC nominal).
TABLE 7. DD-03182 LINE DRIVER SPECIFICATIONS
PARAMETER
UNITS
MIN
TYP MAX
ABSOLUTE MAXIMUM
RATINGS
VOLTAGE BETWEEN
PINS
+V and -V
V1 and GND
VREF and GND
V
V
V
40
7
6
POWER SUPPLY
REQUIREMENTS
+V
-V
V1
VREF (for ARINC 429)
VREF (for other
applications)
THERMAL
Operating Ambient
Temperature
Ceramic
Plastic
Storage Temperature
Lead Temperature
(localized 10 sec
duration)
Thermal Resistance:
Junction to Ambient θja
DD-03182DC
DD-03182PP
DD-03182GP
DD-03182VP
Junction Temperature
VDC
VDC
VDC
VDC
VDC
°C
°C
°C
°C
°C/W
°C/W
°C/W
°C/W
°C
11.4
-11.4
4.75
4.75
0
-55
-40
-65
15 16.5
-15 -16.5
5 5.25
5 5.25
+125
+85
+150
+300
75
95
115
130
175
Note: Refer to DD-03182 data sheet for more information.
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