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PDF S1D13705 Data sheet ( Hoja de datos )
| Número de pieza | S1D13705 | |
| Descripción | Embedded Memory LCD Controller | |
| Fabricantes | Epson Company | |
| Logotipo |  |
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S1D13705 Embedded Memory LCD Controller
www.DataSheet4U.com
S1D13705
TECHNICAL MANUAL
Document No. X27A-Q-001-04
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
1 page  
ENERGY
S AV I N G
EPSON
GRAPHICS
S1D13705 Embedded Memory LCD Controller
S1D13705
February 2001
The S1D13705 is a color/monochrome LCD graphics controller with an embedded 80K Byte SRAM
display buffer. The high integration of the S1D13705 provides a low cost, low power, single chip solution
to meet the requirements of embedded markets such as Office Automation equipment, Mobile Commu-
nications devices, and Palm-size PCs where board size and battery life are major concerns.
Products requiring a “Portrait” display can take advantage of the Hardware Portrait Mode feature of the
S1D13705. Virtual and Split Screen are just some of the display modes supported. While focusing on
www.DataSheet4U.cdoemvices targeted by the Microsoft Windows CE Operating System, the S1D13705’s impartiality to CPU
type or operating system makes it an ideal display solution for a wide variety of applications.
■ FEATURES
• Embedded 80K byte SRAM display buffer.
• Direct support for the following CPU’s:
Hitachi SH-3.
Hitachi SH-4.
Motorola M68xxx.
MPU bus interface with programmable
READY.
• Resolutions up to:
640x480 at a color depth of 2 bpp.
640x240 at a color depth of 4 bpp.
320x240 at a color depth of 8 bpp.
• Up to 256 simultaneous colors from a possible
4096 colors on passive LCD panels and active
matrix TFT/D-TFD LCD panels.
• Register level support for EL panels.
• Hardware Portrait Mode
• Split Screen Display
• Virtual Display Support
• LCD power-down sequencing.
■ SYSTEM BLOCK DIAGRAM
CPU
X27A-C-001-04
Data and
Control Signals
Digital Out
S1D13705
Flat Panel
1
5 Page 
Epson Research and Development
Vancouver Design Center
Page 5
List of Tables
Table 5-1: Summary of Power On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5-2: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5-3: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6-2: Recommended Operating Conditions for Core VDD = 3.3V ± 10% . . . . . . . . . . . 24
Table 6-3: Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 6-4: Output Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7-1: SH-4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7-2: SH-3 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Table 7-3: MC68K #1 Bus Timing (MC68000) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7-4: MC68K #2 Timing (MC68030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7-5: Generic #1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7-6: Generic #2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7-7: Clock Input Requirements for CLKI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7-8: Clock Input Requirements for BCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7-9: LCD Panel Power On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7-10: Power Down/Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7-11: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7-12: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7-13: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7-14: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 45
Table 7-15: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 47
Table 7-16: Dual Monochrome 8-Bit Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . 49
Table 7-17: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 7-18: TFT/D-TFD A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 8-1: Panel Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 8-2: Gray Scale/Color Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 8-3: High Performance Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 8-4: Inverse Video Mode Select Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 8-5: Hardware Power Save/GPIO0 Operation . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 8-6: Software Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 8-7: Selection of SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 8-8: Selection of PCLK and MCLK in SwivelView Mode . . . . . . . . . . . . . . . . . . . 68
Table 12-1: Default and Alternate SwivelView Mode Comparison . . . . . . . . . . . . . . . . . . 81
Table 13-1: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 13-2: Software Power Save Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 13-3: Hardware Power Save Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 13-4: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 13-5: S1D13705 Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Hardware Functional Specification
Issue Date: 02/02/01
S1D13705
X27A-A-001-10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S1D13705.PDF ] | |
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