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PDF ICS840004I-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS840004I-01 | |
| Descripción | CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840004I-01
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS840004I-01 is a 4 output LVCMOS/LVTTL
ICS Synthesizer optimized to generate Ethernet
HiPerClockS™ reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from ICS. Using a 25MHz, 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL1:0):
156.25MHz, 125MHz, and 62.5MHz. The ICS840004I-01 uses
www.DataSheeItC4US.’c3ormd generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840004I-01 is
packaged in a small 20-pin TSSOP package.
FEATURES
• Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following output frequencies:
156.25MHz, 125MHz and 62.5MHz
• RMS phase jitter @ 156.25MHZ (1.875MHz - 20MHz):
0.52ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
F_SEL1
0
F_SEL0
0
Inputs
M Divider N Divider
Value
Value
25 4
0 1 25
5
10
25
10
1 1 25
5
M/N
Ratio Value
6.25
5
2.5
5
Output Frequency (MHz)
(25MHz Ref.)
156.25
125
62.5
125
BLOCK DIAGRAM
OE Pullup
F_SEL1:0 Pullup:Pullup
nPLL_SEL Pulldown
nXTAL_SEL Pulldown
XTAL_IN 25MHz
OSC 0
XTAL_OUT
TEST_CLK Pulldown
1
2
Phase
Detector
VCO
F_SEL1:0
1N
0 0 ÷4
0 1 ÷5
0 1 0 ÷10
1 1 ÷5
M = ÷25 (fixed)
PIN ASSIGNMENT
F_SEL0 1 20 F_SEL1
nc 2 19 GND
nXTAL_SEL 3 18 Q0
TEST_CLK 4 17 Q1
OE 5
1 6 VDDO
MR 6 15 Q2
nPLL_SEL 7 14 Q3
VDDA 8
13 GND
nc 9 12 XTAL_IN
Q0 VDD 10 11 XTAL_OUT
ICS840004I-01
Q1
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
Q2 package body
G Package
Q3 Top View
MR Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840004AGI-01
www.icst.com/products/hiperclocks.html
REV. A JUNE 28, 2005
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840004I-01
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 2
156.25
125
62.5
TBD
MHz
MHz
MHz
ps
www.DataSheet4tjUit(.cØo)m
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
0.48
0.59
0.53
ps
ps
ps
tL PLL Lock Time
TBD
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
450
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
ms
ps
%
TABLE
5C.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
V
DDO
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical
156.25
fOUT Output Frequency
125
62.5
tsk(o) Output Skew; NOTE 1, 2
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, (1.875MHz - 20MHz)
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
0.50
0.60
0.51
tL PLL Lock Time
TBD
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
450
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
ms
ps
%
840004AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A JUNE 28, 2005
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