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PDF ICS840014I Data sheet ( Hoja de datos )

Número de pieza ICS840014I
Descripción CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Fabricantes Integrated Circuit Systems 
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840014I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS840014I is a 4 output LVCMOS/LVTTL
ICS Synthesizer optimized to generate Fibre Channel
HiPerClockS™ reference clock frequencies and is a member of
the HiPerClocksTM family of high performance
clock solutions from ICS. This device uses a
26.5625MHz, 18pF parallel resonant crystal to synthesize
106.25MHz. Using FemtoClock’sTM ultra-low phase noise VCO
technology, the ICS840014I can achieve 1ps or lower typical
www.DataSheerta4nUd.coomm rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS840014I is packaged in a small 20-pin
TSSOP package.
FEATURES
• Four LVCMOS/LVTTL outputs, 15typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Output frequency: 106.25MHz or 53.125MHz
• RMS phase jitter @ 106.25MHz (637KHz - 5MHz):
0.72ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
26.5625
26.5625
Inputs
F_SEL1
M Divider
Value
N Divider
Value
0 24
6
1 24
12
M/N
Ratio Value
4
2
Output
Frequency
Range
106.25
53.125
BLOCK DIAGRAM
OE Pullup
Pullup
F_SEL
nPLL_SEL Pulldown
nXTAL_SEL Pulldown
XTAL_IN 26.5625MHz
OSC 0
XTAL_OUT
TEST_CLK Pulldown
1
Phase
Detector
VCO
F_SEL
1 0 ÷6
1 ÷12
0
M = ÷24 (fixed)
PIN ASSIGNMENT
F_SEL 1 20 nc
nc 2 19 GND
nXTAL_SEL 3 18 Q0
TEST_CLK 4 17 Q1
OE 5
1 6 VDDO
MR 6 15 Q2
nPLL_SEL 7 14 Q3
VDDA 8
13 GND
Q0 nc 9 12 XTAL_IN
VDD 10 11 XTAL_OUT
Q1 ICS840014I
20-Lead TSSOP
Q2 6.5mm x 4.4mm x 0.92mm
package body
Q3 G Package
Top View
MR Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
1

1 page




ICS840014I pdf
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840014I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
fOUT Output Frequency
106.25
53.125
tsk(o) Output Skew; NOTE 1, 3
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
106.25MHz (637KHz - 5MHz)
53.125MHz (637KHz - 5MHz)
0.75
0.63
www.DataSheet4tLU.com PLL Lock Time
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
550
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
1
Units
MHz
MHz
ps
ps
ps
ms
ps
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
fOUT Output Frequency
106.25
53.125
tsk(o) Output Skew; NOTE 1, 3
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
106.25MHz (637KHz - 5MHz)
53.125MHz (637KHz - 5MHz)
0.72
0.63
tL PLL Lock Time
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
500
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
1
Units
MHz
MHz
ps
ps
ps
ms
ps
%
TABLE 5C. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
fOUT Output Frequency
106.25
53.125
tsk(o) Output Skew; NOTE 1, 3
TBD
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
106.25MHz (637KHz - 5MHz)
53.125MHz (637KHz - 5MHz)
0.72
0.67
tL PLL Lock Time
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
500
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V /2.
DDO
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
1
Units
MHz
MHz
ps
ps
ps
ms
ps
%
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
5

5 Page





ICS840014I arduino
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS840014I
FEMTOCLOCKS™CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS840014AGI
ICS840014AGIT
Marking
TBD
TBD
Package
20 Lead TSSOP
20 Lead TSSOP on Tape and Reel
Count
72 per tube
2500
Temperature
-40°C to 85°C
-40°C to 85°C
www.DataSheet4U.com
The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
840014AGI
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 23, 2004
11

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