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PDF DS32EV400 Data sheet ( Hoja de datos )
| Número de pieza | DS32EV400 | |
| Descripción | Programmable Single Equalizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2007
DS32EV400
Programmable Quad Equalizer
General Description
The DS32EV400 programmable quad equalizer provides
compensation for transmission medium losses and reduces
the medium-induced deterministic jitter for four NRZ data
channels. The DS32EV400 is optimized for operation up to
3.2 Gbps for both cables and FR4 traces. Each equalizer
channel has eight levels of input equalization that can be pro-
grammed by three control pins, or individually through a Serial
www.DataSheeMt4aUn.caogmement Bus (SMBus) interface.
The equalizer supports both AC and DC-coupled data paths
for long run length data patterns such as PRBS-31, and bal-
anced codes such as 8b/10b. The device uses differential
current-mode logic (CML) inputs and outputs, and is available
in a 7 mm x 7 mm 48-pin leadless LLP package. Power is
supplied from either a 2.5V or 3.3V supply.
Features
■ Equalizes up to 14 dB loss at 3.2 Gbps
■ 8 levels of programmable equalization
■ Settable through control pins or SMBus interface
■ Operates up to 3.2 Gbps with 40” FR4 traces
■ 0.12 UI residual deterministic jitter at 3.2 Gbps with 40”
FR4 traces
■ Single 2.5V or 3.3V power supply
■ Signal Detect for individual channels
■ Standby mode for individual channels
■ Supports AC or DC-Coupling with wide input common-
mode
■ Low power consumption: 375 mW Typ at 2.5V
■ Small 7 mm x 7 mm 48-pin LLP package
■ 9 kV HBM ESD
■ -40 to 85°C operating temperature range
Simplified Application Diagram
© 2007 National Semiconductor Corporation 300319
30031924
www.national.com
1 page  
Symbol
Parameter
Conditions
VDDTX
Suplly Voltage of Transmitter to DC-Coupled Requirement
EQ (Note 9)
VICMDC
Input Common Mode Voltage
DC-Coupled Requirement
Differential measurement at point
A
(Figure 1)
(Note 7)
RLI
Differential Input Return Loss
100MHz – 1.6GHz, with fixture’s
effect de-embedded
RIN Input Resistance
CML OUTPUTS (OUT_n+, OUT_n-)
Differential across IN+ and IN-
VO Output Voltage Swing
Differential measurement with
OUT+ and OUT- terminated by
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50Ω to GND AC-Coupled
(Figure 2)
VOCM
Output Common Mode Voltage
Single-ended measurement DC-
Coupled with 50Ω terminations
(Note 7)
tR, tF
Transition Time
20% to 80% of differential output
voltage, measured within 1” from
output pins.
(Figure 2)
(Note 7)
RO Output Resistance
Single ended to VDD
RLO Differential Output Return Loss 100 MHz – 1.6 GHz, with fixture’s
effect de-embedded. IN+ = static
high.
tPLHD
tPHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Propagation delay measurement
at 50% VO between input to
output, 100 Mbps
(Figure 3)
(Note 7)
tCCSK
Inter Pair Channel to Channel
Skew
Difference in 50% crossing
between channels
EQUALIZATION
DJ1 Residual Deterministic Jitter at 3.2 40” of 6 mil microstrip FR4,
Gbps
EQ Setting 0x07, PRBS-7 (27-1)
pattern
(Note 5, 6)
DJ2 Residual Deterministic Jitter at 2.5 40” of 6 mil microstrip FR4,
Gbps
EQ Setting 0x07, PRBS-7 (27-1)
pattern
(Note 5, 6)
DJ3 Residual Deterministic Jitter at 1 40” of 6 mil microstrip FR4,
Gbps
EQ Setting 0x07, PRBS-7 (27-1)
pattern
(Note 5, 6)
RJ Random Jitter
(Note 7, 8)
Min
1.6
VDDTX –
0.8
85
500
VDD– 0.2
20
42
Typ
10
100
50
10
240
240
7
0.12
0.1
0.05
0.5
Max
VDD
Units
V
VDDTX –
0.2
V
dB
115 Ω
725 mVP-P
VDD– 0.1
V
60 ps
58 Ω
dB
ps
ps
ps
0.20
UIP-P
0.16
UIP-P
UIP-P
psrms
5 www.national.com
5 Page 
DS32EV400 Applications
Information
The DS32EV400 is a programmable quad equalizer opti-
mized for operation up to 3.2 Gbps for backplane and cable
applications.
DATA CHANNELS
The DS32EV400 provides four data channels. Each data
channel consists of an equalizer stage, a limiting amplifier, a
DC offset correction block, and a CML driver as shown in Fig-
ure 6.
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FIGURE 6. Simplified Block Diagram
30031904
EQUALIZER BOOST CONTROL
Each data channel supports eight programmable levels of
equalization boost. The state of the FEB pin determines how
the boost settings are controlled. If the FEB pin is held High,
then the equalizer boost setting is controlled by the Boost Set
pins (BST_[2:0]) in accordance with Table 2. If this program-
ming method is chosen, then the boost setting selected on the
Boost Set pins is applied to all channels. When the FEB pin
is held Low, the equalizer boost level is controlled through the
SMBus. This programming method is accessed via the ap-
propriate SMBus registers (see Table 1). Using this approach,
equalizer boost settings can be programmed for each channel
individually. FEB is internally pulled High (default setting);
therefore if left unconnected, the boost settings are controlled
by the Boost Set pins (BST_[0:2]). The eight levels of boost
settings enables the DS32EV400 to address a wide range of
media loss and data rates.
TABLE 2. EQ Boost Control Table
6 mil
microstrip
FR4 trace
length (in)
24 AWG
Twin-AX
cable length
(m)
Channel
[BST_2,
Loss at 1.6 BST_1,BST_
GHz (dB)
0]
0 0 0 000
5 2 3 001
10 3
6 010
15 4
7 011
20 5
8 1 0 0 (Default)
25 6 10 1 0 1
30 7 12 1 1 0
40 10 14 1 1 1
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS32EV400.PDF ] | |
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