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PDF UT7R995C Data sheet ( Hoja de datos )
| Número de pieza | UT7R995C | |
| Descripción | RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer | |
| Fabricantes | Aeroflex Circuit Technology | |
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Standard Products
UT7R995 & UT7R995C RadClockTM
RadHard 2.5V/3.3V 200MHz High-Speed
Multi-phase PLL Clock Buffer
Datasheet
February, 2007
FEATURES:
+3.3V Core Power Supply
+2.5V or +3.3V Clock Output Power Supply
www.DataSheet4U- .Icnodmependent Clock Output Bank Power Supplies
Output frequency range: 6 MHz to 200 MHz
Bank pair output-output skew < 100 ps
Cycle-cycle jitter < 50 ps
50% ± 2% maximum output duty cycle at 100MHz
Eight LVTTL outputs with selectable drive strength
Selectable positive- or negative-edge synchronization
Selectable phase-locked loop (PLL) frequency range and
lock indicator
Phase adjustments in 625 to 1300 ps steps up to ± 7.8 ns
(1-6,8,10,12) x multiply and (1/2,1/4) x divide ratios
Compatible with Spread-Spectrum reference clocks
Power-down mode
Selectable reference input divider
Radiation performance
- Total-dose tolerance: 100 krad (Si)
- SEL Immune to a LET of 109 MeV-cm2/mg
- SEU Immune to a LET of 109 MeV-cm2/mg
Military temperature range: -55oC to +125oC
Extended industrial temp: -40oC to +125oC
Packaging options:
- 48-Lead Ceramic Flatpack
Standard Microcircuit Drawing: 5962-05214
- QML-Q and QML-V compliant part
INTRODUCTION:
The UT7R995/UT7R995C is a low-voltage, low-power, eight-
output, 6-to-200 MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance microprocessor and communication sys-
tems.
The user programs both the frequency and the phase of the out-
put banks through nF[1:0] and DS[1:0] pins. The adjustable
phase feature allows the user to skew the outputs to lead or lag
the reference clock. Connect any one of the outputs to the
feedback input to achieve different reference frequency multi-
plication and division ratios.
The devices also feature split output bank power supplies that
enable banks 1 & 2, bank 3, and bank 4 to operate at a different
power supply levels. The ternary PE/HD pin controls the syn-
chronization of output signals to either the rising or the falling
edge of the reference clock and selects the drive strength of the
output buffers. The UT7R995 and UT7R995C both interface
to a digital clock while the UT7R995C will also interface to a
quartz crystal.
4F0
4F1
sOE
PD/DIV
PE/HD
VDD
VDDQ3
3Q1
3Q0
VSS
VSS
VDD
FB
VDD
VSS
VSS
2Q1
2Q0
VDDQ1
LOCK
VSS
DS0
DS1
1F0
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 UT7R995 38
12 & 37
13 UT7R995C 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
3F1
3F0
FS
VSS
VSS
VDDQ4
4Q1
4Q0
VSS
VSS
VDD
XTAL1
NC/XTAL2
VDD
VSS
VSS
1Q1
1Q0
VDDQ1
VSS
TEST
2F1
2F0
1F1
Figure 1. 48-Lead Ceramic Flatpack Pin Description
1
1 page  
Table 10: Output Skew Settings4
Skew
nF[1:0] 1Q[1:0], 2Q[1:0]
Skew
3Q[1:0]
Skew
4Q[1:0]
LL 1, 2 -4tU Divide by 2 Divide by 2
LM -3tU
-6tU -6tU
LH -2tU
ML -1tU
-4tU -4tU
-2tU -2tU
MM
www.DataSheet4MUH.com
Zero Skew
+1tU
Zero Skew
+2tU
Zero Skew
+2tU
HL
HM
HH 2
+2tU
+3tU
+4tU
+4tU
+6tU
Divide by 4
+4tU
+6tU
Inverted 3
Notes:
1. nF[1:0] = LL disables bank specific outputs if TEST=MID and sOE = HIGH.
2. When TEST=MID or HIGH, the Divide-by-2, Divide-by-4, and Inversion-
options function as defined in Table 9.
3. When 4Q[1:0] are set to run inverted (4F[1:0] = HH), sOE disables these out-
puts HIGH when PE/HD = HIGH or MID, sOE disables them LOW when
PE/HD = LOW.
4. Skew accuracy is within +/- 15% of n*tU where "n" is the selected number
of skew steps. Supplied as a design limit, but not tested or guaranteed.
A graphical summary of Table 10 is shown in Figure 3. The
drawing assumes that the FB input is driven by a clock output
programmed with zero skew. Depending upon the state of the
nF[1:0] pins the respective clocks will be skewed, divided, or
inverted relative to the fedback output as shown in Figure 3.
1.3 Output Drive, Synchronization, and Power Supplies:
The UT7R995/C employs flexible output buffers providing the
user with selectable drive strengths, independent power sup-
plies, and synchronization to either edge of the reference input.
Using the 3-level PE/HD pin, the user selects the reference edge
synchronization and the output drive strength for all clock out-
puts. The options for edge synchronization and output drive
strength selected by the PE/HD pin are listed in Table 11.
PE/HD
L
M
H
Table 11: PE/HD Settings
Synchronization
Output Drive
Strength 1
Negative
Low Drive
Positive
High Drive
Positive
Low Drive
Notes:
1. Please refer to "DC Parameters" section for IOH/IOL specifications.
1F[1:0] 2F[1:0] 3F[1:0] 4F[1:0]
XTAL1 Input
FB Input
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LM
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
HM
LL/HH LL
(N/A) HH
-6tU
-4tU
-3tU
-2tU
-1tU
0tU
+1tU
+2tU
+3tU
+4tU
+6tU
DIVIDED
INVERTED
Figure 3. Typical Outputs with FB Connected to a Zero-Skewed Output
5
5 Page 
6.0 DC INPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = +3.3V + 0.3V; TC = -55°C to +125°C) (For "W" screening, TC = -40°C to +125°C)
Symbol
Description
Conditions
Min.
Max. Units
VIH 4
VIL 4
VIHH 1, 3
VIMM 1, 3
www.DataSheeVt4IUL.Lco1,m3
IIL
I3L 1
IDDPD
CIN-2L 2
CIN-3L 2
High-level input voltage
(XTAL1, FB and sOE inputs)
Low-level input voltage
(XTAL1, FB and sOE inputs)
High-level input voltage
Mid-level input voltage
Low-level input voltage
Input leakage current
(XTAL1, FB and sOE inputs)
VIN = VDD or VSS; VDD = Max
HIGH, VIN = VDD
3-Level input DC current MID, VIN = VDD/2
Power-down current
LOW, VIN = VSS
VDD = VDDQn = +3.0V;
TEST & sOE = HIGH;
XTAL1, PD/DIV, FB, FS, & PE/
HD = LOW;
All other inputs are floated;
Outputs are not loaded
TC = +25°C
TC = +125°C
TC = -55°C
Input pin capacitance
2-level inputs
f = 1MHz @ 0V; VDD = Max
Input pin capacitance
3-level inputs
f = 1MHz @ 0V; VDD = Max
2.0 -- V
-- 0.8 V
VDD - 0.6
--
VDD÷2 - 0.3 VDD÷2 + 0.3
-- 0.6
V
V
V
-5 5 μA
-- 200 μA
-50 50 μA
-200 -- μA
-- 100 μA
-- 150 μA
-- 4.5 mA
8.5 pF
15 pF
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. These inputs are normally wired to VDD, VSS, or left unconnected. Internal termination resistors bias unconnected inputs to VDD/2 + 0.3V. The 3-level inputs
include: TEST, PD/DIV, PE/HD, FS, nF[1:0], DS[1:0].
2. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
3. Pin FS is guaranteed by functional testing.
4. For pin FB, this specification is supplied as a design limit, but is neither guaranteed nor tested.
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet UT7R995C.PDF ] | |
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