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PDF P4C1024L Data sheet ( Hoja de datos )
| Número de pieza | P4C1024L | |
| Descripción | LOW POWER 128K x 8 CMOS STATIC RAM | |
| Fabricantes | Pyramid Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de P4C1024L (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
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P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
www.DataSheet4UE.caomsy Memory Expansion Using CE1, CE2 and OE
Inputs
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
FUNCTIONAL BLOCK DIAGRAM
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP
locations are specified on address pins A0 to A16. Read-
ing is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE1 or OE is HIGH or WE or CE2 is LOW.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, and a 600 mil PDIP.
PIN CONFIGURATION
DIP (P600, C10), SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document # SRAM125 REV C
Revised September 2006
1
1 page  
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
-55
Min Max
tWC Write Cycle Time
tCW
Chip Enable Time
to End of Write
55
50
tAW
Address Valid to
End of Write
tAS
Address Set-up
Time
50
0
www.DataSheet4U.com tWP
tAH
tDW
tDH
tWZ
tOW
Write Pulse Width
Address Hold
Time
Data Valid to End
of Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
40
0
25
0
5
25
-70
Min
70
Max
60
60
0
50
0
30
0
30
5
WRITE CYCLE NO. 1 (WE CONTROLLED)(6)
P4C1024L
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle.
7. OE is LOW for this WRITE cycle to show twz and tow.
8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM125 REV C
Page 5 of 10
5 Page 
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
REV.
ISSUE
DATE
OR 1997
SRAM125
P4C1024L LOW POWER 128K x 8 CMOS STATIC RAM
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
DAB
New Data Sheet
A
B
www.DataSheet4U.com
C
Oct-05
Feb-06
Sep-06
JDB
JDB
JDB
Change logo to Pyramid
Added TSOP package
Added Ceramic DIP package
P4C1024L
Document # SRAM125 REV C
Page 11 of 10
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet P4C1024L.PDF ] | |
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